Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.

Data communications and storage systems require error control techniques to be transferred successfully without failure. Polar coding has been used as a state-of-the-art forward error correction code for such an error control technique. However, the conventional decoding based on successive cancellation has a drawback in its poor performance and long latency to complete. Because the factor graph of polar codes has a lot of short cycles, a parallelizable belief propagation decoding also does not perform well. The method and system of the present invention provide a way to resolve the issues by introducing a protograph lifting expansion for a polar coding family so that highly parallelizable decoding is realized to achieve a high coding gain and high throughput without increasing the computational complexity and latency. The invention enables an iterative message passing to work properly by eliminating short cycles through a hill-climbing optimization of frozen bits allocation and permutation.

A method and an apparatus are provided for decoding a polar code. A simplified successive cancellation list (SSCL) decoding tree for the polar code is generated. The SSCL decoding tree includes a plurality of nodes. One or more nodes of the plurality of nodes are identified as employing Reed-Muller codes for decoding. Decoding of received log-likelihood ratios (LLRs) is performed using Reed-Muller codes at the one or more nodes. Hard decision values are output from the one or more nodes.

A decoding system and method of a non-volatile memory are provided in which information regarding a characteristic of a non-volatile memory is used to determine an initial log-likelihood-ratio (LLR) table from among a number of LLR tables. The decoding is then performed using the determined initial LLR table.

Provided herein may be an electronic device using an artificial neural network. The electronic device may include a training data generator configured to determine an input vector corresponding to a trapping set, detected during error correction decoding corresponding to a codeword, and a target vector corresponding to the input vector, and a training component configured to train an artificial neural network based on supervised learning by inputting the input vector to an input layer of the artificial neural network and by inputting the target vector to an output layer of the artificial neural network.

A receiving unit (2020) generates a received frame from a modulated optical signal. The modulated optical signal is generated such that a transmission symbol is generated by mapping an encoded bit string obtained by encoding a transmission bit string to an m-dimensional symbol space, a transmission frame is generated by mapping the transmission symbol to an n-dimensional frame space (n<m), and an optical carrier wave is modulated by using the transmission frame. A converting unit (2040) generates candidate vectors (m-dimensional vectors belonging to a partial symbol space within the symbol space) by using a received frame. A first computing unit (2070) computes a probability of that the transmission symbol belonging to the partial symbol space is transmitted for each partial symbol space. A second computing unit (2080) computes a log-likelihood ratio of each bit of the encoded bit string by using the probability.

A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value.

A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.