According to one embodiment, a control unit determines a first physical sector in which first data is to be written among a plurality of physical sectors based on first information that is based on a result of the first data translation and the device characteristics of the plurality of physical sectors. A write unit writes data for which a first data translation is performed into the first physical sector of a nonvolatile memory.

In one example, a device for accessing image data includes a memory configured to store image data and one or more processors configured to code a plurality of bit length values for a plurality of block fixed length code length (bflc_len) values for a plurality of blocks of a tile or sub-tile of an image, the bit length values representing numbers of bits used to code the blfc_len values, code the bflc_len values for each of the plurality of blocks such that the bflc_len values have numbers of bits indicated by the respective bit length values, code the codewords for each of the plurality of blocks such that the codewords have the numbers of bits indicated by the bflc_len values for corresponding blocks of the plurality of blocks, and access the bit length values, the bflc_len values, and the codewords in the memory.

In one example, a device for accessing image data includes a memory configured to store image data and one or more processors configured to code a plurality of bit length values for a plurality of block fixed length code length (bflc_len) values for a plurality of blocks of a tile or sub-tile of an image, the bit length values representing numbers of bits used to code the blfc_len values, code the bflc_len values for each of the plurality of blocks such that the bflc_len values have numbers of bits indicated by the respective bit length values, code the codewords for each of the plurality of blocks such that the codewords have the numbers of bits indicated by the bflc_len values for corresponding blocks of the plurality of blocks, and access the bit length values, the bflc_len values, and the codewords in the memory.

According to an embodiment, a storage control device includes a controller, a compression condition determiner, a compressor, and an error correction encoder. The controller receives a write request for a data item and determines whether or not the wear degree of a target region in a storage device to which the data item is to be written is less than a threshold value. The compression condition determiner determines, based on the wear degree, an optimal compression condition out of compression conditions that include lossy compression. The compressor generates, based on the compression condition, compressed data. The error correction encoder subjects the data item to error correction and generates encoded data.

A method, according to one embodiment, includes selecting, from a buffer, a combination of compressed logical pages of data to maximize an amount of used space in an error correction code container. The method also preferably includes processing the combination of compressed logical pages to generate error correction code data. Furthermore, the method may include writing the data corresponding to the combination of compressed logical pages and the associated error correction code data to a non-volatile random access memory. Other systems, methods, and computer program products are described in additional embodiments.

A method for processing data associated with a data frame. The method includes: providing output data with a plurality of information elements, for example in the form of a bit vector, for example for a device for executing cryptographic functions, wherein a first information element of the plurality of information elements has a length of 11 bits and characterizes first identification information associated with a data frame, wherein a second information element of the plurality of information elements has a length of 18 bits and is designed to characterize optional second identification information associated with the data frame, and, optionally, using the output data.

An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression circuitry to compress a cache line data structure to be written into a system memory. The memory controller logic circuitry has adjustable length ECC information generation circuitry to generate an amount of ECC information for the cache line data structure based on an amount of compression applied to the cache line data structure by the compression circuitry. The memory controller logic having circuitry to implement a write process sequence for the cache line data structure that is specific for the cache line data structure's amount of compression and/or amount of ECC information and to implement a different write process sequence that is specific for another cache line data structure having a different amount of compression and/or ECC information as the cache line data structure.

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword.

Information reduction in data processing environments includes at least one of: one or more Error Correcting Codes that decode n-vectors into k-vectors and utilize said decoding to information-reduce data from a higher dimensional space into a lower dimensional space. The information reduction further provides for a hierarchy of information reduction allowing a variety of information reductions. Transformations are provided to utilize available data space, and data may be transformed using several techniques including windowing functions, filters in the time and frequency domains, or any numeric processing on the data.

A plurality of data words are written into a TCAM; each has binary digits and don't-care digits. Contemporaneously, for each of the words: a first checksum is calculated on the binary digits; and the following are stored in a corresponding portion of a RAM: an identifier of the binary digits and the first checksum. The ternary content-addressable memory is queried with an input word. Upon the querying yielding a match, further steps include retrieving, from the random-access memory, corresponding values of the identifier of the binary digits and the first checksum; computing a second checksum on the input word, using the identifier of the binary digits; and if the second and first checksums are not equal, determining in real time that the match is a false positive.