An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.

A transmitter is provided. The transmitter includes: a segmenter configured to segment information bits into a plurality of blocks based on one of a plurality of preset reference values; an outer encoder configured to encode each of the plurality of blocks to generate first parity bits; and a Low Density Parity Check (LDPC) encoder configured to encode each of the plurality of blocks and the first parity bits to generate an LDPC codeword including second parity bits, wherein the one of the preset reference values is determined depending on at least one of a code rate used to encode each of the plurality of blocks and the first parity bits and whether to perform repetition of at least a part of the LDPC codeword in the LDPC codeword.

A transmission apparatus, in particular for use in a Low Throughput Network, comprises an FEC encoder configured to encode payload data into FEC code words each having a predetermined code word length, and a frame forming section configured to form a frame having a predetermined frame length. A frame comprises a first frame portion having a first predetermined length of an integer multiple of the predetermined code word length and a second frame portion having a second predetermined length shorter than the predetermined code word length. The frame forming section is configured to include an FEC code word and a predetermined number of repetitions of said FEC code word into the first frame portion of a frame and to include a selected number of bits of said FEC code word into the second frame portion of said frame.

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.

A method by which a signal transmission device transmits packets in a communication system is provided. The method includes the operations of, generating a source symbol block including one or more source symbols having the same length by using a source packet block including one or more source packets; generating a restoration symbol block generated using one or more restoration symbols by performing a forward error correction (FEC) coding operation on the source symbol block; generating an FEC source packet including the source packets and an FEC payload identifier (ID) and transmitting the FEC source packet to a lower protocol; generating an FEC restoration packet including one or more of the restoration symbols and the FEC payload ID and transmitting the FEC restoration packet to the lower protocol; and transmitting FEC configuration information including information on the source symbol block generation operation to a receiver.

A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (11-1) of this disclosure, included in a transmission device (1) of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator (23) of this disclosure, included in a reception device (2) of this disclosure, decodes digital data encoded by the encoder (11-1).

A data processing method based on a quasi-cyclic LDPC includes: when a size of service data is less than a magnitude of information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). It ensures that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

This disclosure relates to a 5G or pre-5G communication system for supporting a higher data transfer rate than a 4G communication system such as LTE. The present invention relates to a method for encoding and decoding a channel in a communication or broadcasting system, comprising the steps of: determining an input bit size (CBS); determining a code rate (R); determining a size (Z) of a block; comparing the determined CBS and code rate with predetermined reference values; determining an LDPC sequence to perform LDPC encoding according to the comparison result; and performing LDPC encoding and decoding on the basis of the LDPC sequence and the block size. Further, the present invention comprises the steps of: determining a code rate (R) indicated by a modulation and coding scheme (MCS) index; determining a transport block size; and determining either a first basic matrix or a second basic matrix as a basic matrix on the basis of the transport block size and the code rate.

Technologies for performing encoding of data symbols for column read operations include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to obtain a data set to encode. The data set is defined by a set of data symbols. The circuitry is also configured to determine a set of codewords to encode the data symbols of the data set, including defining each codeword with a set bit distance of at least two from every other codeword in the set of codewords. Additionally, the circuitry is configured to write the data set to the memory as a function of the determined set of codewords.

A method for decoding a channel signal in a signal reception apparatus is provided. The method includes performing a block decoding operation on a channel signal block, and if the block decoding for the channel signal block fails, re-performing a block decoding operation on the channel signal block using a preset pattern.