H03M13/6505

Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Communication control apparatus, radio communication apparatus, communication control method, and radio communication method

In order provide a communication control apparatus, a radio communication apparatus, a communication control method, a radio communication method, and a program that are capable of contributing to improving a radio communication technology related to IDMA, a communication control apparatus is provided. The communication control apparatus includes a communication unit configured to communicate with a radio communication apparatus of a radio communication system using interleave division multiple access (IDMA); and a control unit configured to allocate an interleaver type of an interleaver to be used for IDMA by the radio communication apparatus.

Systems and methods for piece-wise rate matching when using polar codes

Systems and methods are disclosed that relate to performing rate matching when using polar codes. In one embodiment, a plurality of bits are received at a polar encoder. A value is obtained that corresponds to at least one of: a coding rate to be used to transmit the plurality of bits, and a number of coded bits to be used to transmit the plurality of bits. It is determined which range of values the value falls within, and an information sequence is obtained that corresponds to the range the value falls within. The plurality of bits are mapped to a subset of positions of an input vector according to the information sequence. The remaining positions of the input vector are set as frozen values that are known by a decoder. The input vector is then encoded in the polar encoder to generate a codeword.

METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES
20200052817 · 2020-02-13 ·

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Sequential decoding with stack reordering

There is provided a decoder (310) for sequentially decoding a data signal received through a transmission channel in a communication system, the received data signal carrying transmitted symbols, the decoder comprising a symbol estimation unit (311) configured to determine estimated symbols representative of the transmitted symbols carried by the received signal from information stored in a stack, the stack being filled by iteratively expanding child nodes of a selected node of a decoding tree comprising a plurality of nodes, each node of the decoding tree corresponding to a candidate component of a symbol of the received data signal and each node being associated with a predetermined metric, the stack being filled at each iteration with at least some of the expanded child nodes and being ordered by increasing values of the metrics associated with the nodes, the selected node for each iteration corresponding to the node having the lowest metric in the stack. The decoder further comprises a stack reordering activation monitoring unit (313) configured to monitor at least one stack reordering activation condition and, in response to a stack reordering activation condition being verified, to cause the symbol estimation unit to: reduce the metric associated with each node stored in the stack by a quantity, reorder the stack by increasing value of the reduced metric, and remove a set of nodes from the reordered stack so as to maintain a number N of nodes in the reordered stack, the maintained nodes corresponding to the N nodes having the lowest metrics in the reordered stack.

Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method by a transmitting device generally includes selecting a first lifting size value and a first set of lifting values; generating a first lifted LDPC code by applying the first set of lifting values to interconnect edges in copies of a parity check matrix (PCM) having a first number of variable nodes and a second number of check nodes; determining a second set of lifting values for generating a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Memory system

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

MEMORY SYSTEM

In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes

Certain aspects of the present disclosure generally relate to techniques for compactly describing lifted low-density parity-check (LDPC) codes. A method for wireless communications by a transmitting device is provided. The method generally includes selecting a first lifting size value Z and a first set of lifting values for generating a first lifted LDPC code; generating the first lifted LDPC code by applying the first set of lifting values to interconnect edges in Z copies of a base parity check matrix (PCM) having a first number of base variable nodes and a second number of base check nodes to obtain a first lifted PCM corresponding to the first lifted LDPC code; determining a second set of lifting values for generating second lifted PCM corresponding to a second lifted LDPC code for a second lifting size value based on the first lifted PCM and the first set of lifting values; encoding a set of information bits based on at least one of: the first lifted LDPC code or the second lifted LDPC code to produce a code word; and transmitting the code word.

Systems and methods for latency based data recycling in a solid state memory system

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.