This application relates to communicating information between communication devices. A channel coding method is disclosed. A communication device obtains an input sequence of K bits. The communication device encodes the input sequence using a low density parity check (LDPC) matrix H, to obtain an encoded sequence. The LDPC matrix H is determined according to a base matrix and a lifting factor Z. The base matrix includes m rows and n columns, m is greater than or equal to 5, and n is greater than or equal to 27. The lifting factor Z satisfies a relationship of 22*Z≥K. According to the encoding method provided in the embodiments, information bit sequences of a plurality of lengths can be encoded for transmission between the communication devices.

Provided are a processing method and device for quasi-cyclic low density parity check (LDPC) coding. The processing method for LDPC coding includes: determining, according to a data feature of an information bit sequence to be encoded, a processing strategy for the quasi-cyclic LDPC coding according to a data feature of an information bit sequence to be encoded; and performing, according to the processing strategy and based on a base matrix and a lifting size, the quasi-cyclic LDPC coding and rate matching output on the information bit sequence according to the processing strategy, a base matrix and a lifting value. This technical solution is able to improve adaptability and flexibility of the quasi-cyclic LDPC coding.

Embodiments of this application disclose a communication method and a communications apparatus. The method includes: determining an encoding matrix type of a first sequence based on a modulation and encoding scheme (MCS) index, where the first sequence is obtained after code block segmentation is performed on a second sequence, a length of the second sequence is related to the MCS index, and a length of the first sequence is less than or equal to a first threshold; and encoding the first sequence based on the encoding matrix associated with the encoding matrix type. According to the application, the encoding matrix type can be properly selected for encoding.

Apparatuses and methods are disclosed for determining a transport block size (TBS) as a function of various parameters without cyclic dependencies between the parameters and TBS. The disclosed function can determine a TBS in a single pass, and the determined TBS allows the use of code blocks with equal code block size (CBS) in a transport block segmentation process. The determined TBS can provide byte-aligned code block lengths and require no padding bits in a transport block.

A method includes receiving a first data frame and a second data frame from a communication channel; decoding the first data frame using a first portion of an extended parity-check matrix (PCM); and decoding the second data frame using a second portion of the extended PCM. The first portion is a subset of the second portion.

A memory module includes logic elements that are configurable to a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode data such that any errors can be later identified and corrected. The approach allows a memory module or computing device to be configured to a specific ECC implementation without requiring requests to be sent back and forth between a host.

A decoding circuit system includes a load balancing scheduler circuit, a full range decoder circuit, and an auxiliary decoder circuit. The load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit. The full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data. The load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the auxiliary decoder circuit. The auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data.

Certain aspects of the present disclosure relate to methods and apparatus for optimizing delivery of a transport block (TB) using code rate dependent segmentation.

A transmitter according to the disclosure includes: an encoding unit that generates a code word by performing coding with a low-density parity-check code using a check matrix, the encoding unit being capable of switching the check matrix for use in generating the code word, between a first check matrix with a first code rate and a second check matrix with a second code rate smaller than the first code rate, the first check matrix containing a plurality of cyclic permutation matrices, the encoding unit generating the second check matrix by masking the cyclic permutation matrix at a predetermined position in the first check matrix and adding a row with a column weight equal to or less than a threshold; and a transmission unit that transmits the code word.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARD) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.