An error correction decoding apparatus includes column operators 201 and row operators 211 to 213 provided respectively in accordance with the columns and rows of a check matrix of an LDPC code. A received LLR (log-likelihood ratio) of a received sequence is input into the column operators 201 together with row LLRs from the row operators 211 to 213, whereupon the column operators 201 calculate a total value z.sub.1 of the received LLR of the received sequence and the row LLRs from the row operators 211 to 213. The row operators 211 to 213 hold operation results relating to row LLRs or column LLRs obtained during a previous operation, calculate column LLRs using the total value input from the column operators 201 and the held operation results, calculate row LLRs from the calculated column LLRs, and output the calculated row LLRs to the column operators 201.

A decoding method, a memory control circuit unit and a memory storage device are provided. The decoding method includes: transmitting a read command sequence for reading a plurality of memory cells in order to obtain a plurality of bits, and obtaining a plurality of reliability information corresponding to each of the bits. The decoding method also includes: calculating a sum of a plurality of reliability information matching a check condition among the plurality of reliability information, and adding a balance information to the sum in order to obtain a weight corresponding to a first bit among the bits and a first syndrome. The decoding method further includes: determining whether the bits have at least one error, and if the bits have the at least one error, executing an iteration decoding procedure according to the weight.

The invention relates to the field of decoders, more specifically, to a decoding method of LDPC (Low Density Parity Check Code). The decoding method comprising: in the rwsr (Row-Wise Scanning Round) phase, the recovery circuit reads a plurality of sign bits, the absolute value of a minimum value, the absolute value of a second smallest value and the absolute value of a third smallest value which are stored previously, and they are output by a comparison and a selector, the output of the comparator and selector is shifted, and then is combined with each sign bit to obtain an update message of the previous check node, the update message is subtracted from the posterior probability by the addition circuit to obtain an input of the update unit.

Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

A method for decoding a received code using a device that includes: an antenna for receiving a signal over a wireless channel, and instances of a Maximum-A-Posteriori (MAP) turbo decoder for decoding a segment of the received code, are disclosed. For example, the method, by forward and backward gamma engines, for each window, concurrently computes gamma branch metrics in forward and backward directions, respectively, by forward and backward state metric engines comprising respective lambda engines and coupled to the respective gamma engines, for each window, sequentially computes forward and backward state metrics, respectively, based on respective gamma branch metrics and respective initial values, by the lambda engines, determines Log Likelihood Ratios (LLRs) and soft decisions, and by a post-processor, computes extrinsic data based on the forward and backward state metrics for any subsequent iteration as at least a portion of the a-priori information and otherwise provides a decoded segment.

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

A receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

In some embodiments of the present invention, a data storage device includes a controller and a memory. The data storage device further includes an LDPC encoder and decoder, with the decoder implementing a dynamic precision-rescaling technique for improving performance. In one embodiment, the technique works by rescaling the binary representations of the input log-likelihood ratios (LLRs) and messages upon activation of decoder-state-based triggers. Various triggering functions are introduced, e.g., checking if the number of output LLRs smaller than a certain limit crosses a threshold, checking if the weight of a syndrome crosses a threshold, etc. This technique offers an improvement in the performance of the decoder.