A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding.

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.

A method for decoding a codeword transmitted over a channel demodulates data received over the channel to produce an initial estimate of belief messages for bits of the codeword and decodes the codeword using a belief propagation (BP) decoding that iteratively passes the belief messages between a set of variable nodes representing the bits of the codeword and a set of check nodes representing parity-check constraints on the bits of the codeword until a termination condition is met. The BP decoding selects a look-up table based on a probability of the belief messages and maps, using the look-up table, values of at least two incoming belief messages to values of at least one outgoing belief message that forms an incoming belief message in a subsequent iteration of the BP decoding.

A decoding method for an iterative message-passing based decoder, such as a low-density parity-check (LDPC) decoder, includes calculating syndrome information for a received word, and initializing variable nodes based on the received word. Each received bit of the received word may be represented by a Likelihood-Ratio (LR) or Log-Likelihood-Ratio (LLR) at a respective variable node. Further, the method includes iteratively updating check nodes, and updating the LRs of variable nodes using the syndrome information, determining an error vector from the LRs of the variable nodes, and determining a transmitted word, corresponding to the received word, by subtracting the error vector from the received word. The syndrome information is calculated based upon a parity check matrix.

An apparatus includes a memory and a controller. The memory may be configured to store data. The memory generally comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to generate a set of converted log likelihood ratios by scaling a set of original log likelihood ratios using a selected scalar value, wherein the controller determines the selected scalar value by generating a plurality of sets of scaled log likelihood ratios by scaling the set of original log likelihood ratios with a plurality of corresponding scalar values, calculating a plurality of respective correlation coefficients each measuring a similarity of a respective set of scaled log likelihood ratios to the set of original log likelihood ratios, and selecting the scalar value corresponding to the set of scaled log likelihood ratios whose respective correlation coefficient is highest as the selected scalar value.

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing data to and accessing data from a flash memory.

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

Embodiments are related to systems and methods for data storage, and more particularly to systems and methods for storing and accessing data from a flash memory.

An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value.