An RF receiver includes a low-noise amplifier (LNA) to receive and amplify RF signals, a transformer-based IQ generator circuit, one or more load resisters, one or more mixer circuit, and a downconverter. The transformer-based IQ generator is to generate a differential in-phase local oscillator (LOI) signal and a differential quadrature (LOQ) signal based on a local oscillator (LO) signal received from an LO. The load resisters are coupled to an output of the transformer-based IQ generator. Each of the load resisters is to couple one of the differential LOI and LOQ signals to a predetermined bias voltage. The mixers are coupled to the LNA and the transformer-based IQ generator to receive and mix the RF signals amplified by the LNA with the differential LOI and LOQ signals to generate an in-phase RF (RFI) signal and a quadrature RF (RFQ) signal. The downconverter is to down convert the RFI signal and the RFQ signal into IF signals.

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

Techniques related to signal processing include setting up a first operation mode or a second operation mode. In the first operation mode: providing a first analog signal to a first A/D converter by a first switch and a second analog signal to a second A/D by second switch, and converting the first analog signal to a first digital signal by the first A/D and the second analog signal to a second digital signal by the second A/D. In the second operation mode: demodulating a third analog signal to an in-phase signal and a quadrature signal by an I-Q-demodulator, providing the in-phase signal to the first A/D by the first switch, providing the quadrature signal to a second A/D by second switch, converting the in-phase signal to a third digital signal by the first A/D, and converting the quadrature signal to a fourth digital signal by the second A/D.

In some implementations, a communication device, includes a printed circuit board comprising conductors routed to support a plurality of different configurations of modulation and/or demodulation functionality. The printed circuit board can have multiple analog output interfaces and one or more analog input interfaces, multiple digital network interfaces, and sockets for components including a controller, multiple processors, digital-to-analog converters (DACs), and an analog-to-digital converter (ADC). Various processor sockets are interconnected to support the processors in different sockets selectively being used for different functions, e.g., as a modulator, burst processor, channelizer, etc.

This disclosure relates to a data processing device, comprising: a digital front end (DFE) configured to convert an antenna signal to digital data, wherein the digital data comprises a plurality of data symbols; a baseband (BB) circuitry configured to process the digital data in baseband; and a digital interface between the DFE and the BB circuitry, wherein the DFE comprises a data compression circuitry configured to compress the plurality of data symbols for use in transmission via the digital interface to the BB circuitry.

Systems, methods, and computer program product embodiments are disclosed for processing and displaying multiple signals in near real-time. An embodiment operates by processing, using a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal. The embodiment also processes, using a second DSP of a second signal module, a second packet associated with a second signal. The embodiment equalizes a first processing delay associated with the first DSP with a second processing delay associated with the second DSP such that the first DSP completes processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet. The embodiment then displays the processed first packet approximately simultaneously with the display of the processed second packet.

Systems, methods, and computer program product embodiments are disclosed for processing and displaying multiple signals in near real-time. An embodiment operates by processing, using a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal. The embodiment also processes, using a second DSP of a second signal module, a second packet associated with a second signal. The embodiment equalizes a first processing delay associated with the first DSP with a second processing delay associated with the second DSP such that the first DSP completes processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet. The embodiment then displays the processed first packet approximately simultaneously with the display of the processed second packet.

Techniques related to signal processing include setting up a first operation mode or a second operation mode. In the first operation mode: providing a first analogue signal to a first A/D converter by a first switch and a second analogue signal to a second A/D by second switch, and converting the first analogue signal to a first digital signal by the first A/D and the second analogue signal to a second digital signal by the second A/D. In the second operation mode: demodulating a third analogue signal to an in-phase signal and a quadrature signal by an I-Q-demodulator, providing the in-phase signal to the first A/D by the first switch, providing the quadrature signal to a second A/D by second switch, converting the in-phase signal to a third digital signal by the first A/D, and converting the quadrature signal to a fourth digital signal by the second A/D.

A radio signal processing method and apparatus includes first receiving a receive command that is sent by a router and that carries a receive frequency and a sampling frequency; receiving a radio signal corresponding to the receive frequency according to the receive frequency; performing sampling processing on the radio signal according to the sampling frequency to obtain a digital signal, and sending the digital signal to the router.

An Interleaved Radio Frequency Digital-to-Analog Converter (RF DAC) suitable for use in cellular base stations and optimized to give both a wide RF tuning range and a wide RF bandwidth is disclosed. The RF DAC uses two levels of interleaving, the first providing a direct conversion path from Base Band (BB) to RF, and the second providing a variable interleaving factor through the use of summation to optimize the output bandwidth as a function of the RF center frequency. Digital Interpolation, including an arbitrary sample rate conversion filter, allows the RF DAC to operate from a wide range of possible BB sample rates and the DAC sample rate is a fixed ratio of the RF center frequency. As a result, the spurious outputs from the RF DAC are in known locations that are relatively easy to filter out, minimizing the frequency planning tasks required for a complete RF system design.