A configuration to reduce a UE PAPR due to a transmission of a PAPR reduction signal into a UE null space. The apparatus establishes a connection with a base station. The apparatus transmits, to the base station, an SFMT report including an indication of a capability of the UE to process a signal form the base station that includes an SFMT transmission. The apparatus receives, from the base station, a downlink PAPR reduction signal based on the SFMT report of the UE.

A low voltage drive circuit (LVDC) includes a drive sense circuit operable to convert analog outbound data into an analog transmit signal and convert analog receive signals into analog inbound data, a transmit digital to analog circuit operable to convert transmit digital data into the analog outbound data, and a receive analog to digital circuit including an analog to digital converter, a digital filtering circuit, and a data formatting module. The data formatting module includes a sample and hold circuit operable to sample and hold an n-bit digital value of filtered digital data from the digital filtering circuit to produce an n-bit sampled digital data value, a digital to digital converter circuit operable to adjust formatting of the n-bit sampled digital data value to produce a formatted digital value, and a data packeting circuit operable to generate a packet of received digital data from a plurality of formatted digital values.

A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

A communication system is provided, which includes a power amplifier, a receive-end filter, an ADC, an output simulation circuit, and a predistortion circuit. The power amplifier amplifies a RF input signal to generate a RF output signal. The RF input signal is generated according to a baseband signal. The receive-end filter filters a feedback signal generated according to the RF output signal to output a filtered feedback signal. A bandwidth of the filtered feedback signal is at least 3 to 5 times a bandwidth of the RF input signal. The ADC converts the filtered feedback signal to a digital input signal. The output simulation circuit generates, according to the digital input signal and the baseband signal, a reference signal simulating the RF output signal. The predistortion circuit builds a predistortion model according to the reference signal.

A digital predistortion linearization method is provided for increasing the instantaneous or operational bandwidth for RF power amplifiers employed in wideband communication systems. Embodiments of the present invention provide a method of increasing DPD linearization bandwidth using a feedback filter integrated into existing digital platforms for multi-channel wideband wireless transmitters. An embodiment of the present invention utilizes a DPD feedback signal in conjunction with a low power band-pass filter in the DPD feedback path.

A system and method for communication of digital data includes receiving a plurality of data bits to be transmitted, and generating an output signal for transmission by a transmitter circuit. The generating includes generating a portion of the output signal comprising values of the output signal with magnitude less than a specified threshold, the specified threshold corresponding to a specified transmitter circuit maximum output power; and generating a portion of the output signal comprising a representation of values of the output signal with magnitude greater than the specified threshold.

A method for digital resampling in a digital communications receiver is described. The method comprises selecting whole samples of a received input signal in the time domain and implementing sub-sample digital interpolation in the frequency domain. This amounts to performing the time shift of the interpolation process in the frequency domain. The method may be performed in conjunction with the operation of a polarisation recovery filter. A digital communications receiver is also provided the receiver being arranged to perform frequency domain sub-sample interpolation on an input data signal.

A method for digital resampling in a digital communications receiver is described. The method comprises selecting whole samples of a received input signal in the time domain and implementing sub-sample digital interpolation in the frequency domain. This amounts to performing the time shift of the interpolation process in the frequency domain. The method may be performed in conjunction with the operation of a polarisation recovery filter. A digital communications receiver is also provided the receiver being arranged to perform frequency domain sub-sample interpolation on an input data signal.

A digital-to-analog conversion system is provided. The digital-to-analog conversion system includes a digital-to-analog converter configured to receive a pre-distorted digital signal from a digital circuit, and to generate an analog signal based on the pre-distorted digital signal. Further, the digital-to-analog conversion system includes a feedback loop for providing a digital feedback signal to the digital circuit. The feedback loop includes an analog-to-digital converter configured to generate the digital feedback signal based on the analog signal, and wherein a sample rate of the analog-to-digital converter is lower than a sample rate of the digital-to-analog converter.

Described herein is an improved apparatus for increasing the performance of a modulator, which may function as an ADC. In one embodiment, the modulator comprises a voltage to current converter, a capacitor connected between two outputs of the voltage to current converter to receive a differential input current, and a switch that can switch between connecting each output of the voltage to current converter to ground while disconnecting the other output of the voltage to current converter. In this embodiment, the modulator has no common mode control loop, and no reference current. This results in decreased complexity, i.e., fewer components, as well as reduced noise.