Patent classifications
H04B1/0042
Systems and methods for delta-sigma digitization
A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.
Secure radio methods and apparatus
The present application describes a computer-implemented method for frequency hopping including configuring a radio front end to operate on a first frequency; receiving a transmit signal in a first path in the radio front end; amplifying a transmit signal in the first path; phase shifting the transmit signal in a second path in the radio front end, the second path being different from the first path; coupling the amplified transmit signal to a third path in the radio front end; coupling the phase-shifted transmit signal in the second path to the amplified transmit signal in the third path to form a carrier-cancelled signal in a fourth path in the radio front end in the radio front end; phase shifting the carrier-cancelled signal in the fourth path; coupling the phase-shifted carrier-cancelled signal in the fourth path to the amplified transmit signal in the first path; and reconfiguring the radio front end to operate on a second frequency.
Self-interference channel estimation system and method
The present application describes a self-interference channel estimation system. The system includes a signal generator configured to generate a swept tone having a frequency ranging from an upper edge of a reception band to a lower edge of the reception band, and configured to generate a message signal. The system includes an infinite impulse response (IIR) filter configured to determine an infinite impulse response of a self-interference channel based upon the swept tone. The system includes a processor configured to characterize the self-interference channel based upon the infinite impulse response.
EFFICIENT POLYPHASE ARCHITECTURE FOR INTERPOLATOR AND DECIMATOR
Apparatuses (and methods of manufacturing same), systems, and methods concerning polyphase digital filters are described. In one aspect, an apparatus is provided, including at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients. In one aspect, the apparatus is a polyphase finite impulse response (FIR) digital filter, including an interpolator and a decimator, where each of the interpolator and the decimator have at least one pair of subfilters, each having symmetric coefficients, and a lattice comprising two adders and feedlines corresponding to each of the at least one pair of subfilters, each having symmetric coefficients.
RADIO FREQUENCY MODULE
An amplifier circuit unit of a radio frequency module is mounted on a substrate with a first external terminal interposed therebetween, a switch circuit unit is mounted on the substrate with a second external terminal interposed therebetween, and a matching circuit unit is mounted on the substrate with a first terminal and a second terminal interposed therebetween. The first terminal is electrically connected to the second external terminal of the switch circuit unit, and the second terminal is electrically connected to the first external terminal of the amplifier circuit unit. When viewed from a direction perpendicular to one main surface of the substrate, the first terminal is superposed with the second external terminal of the switch circuit unit, and the second terminal is superposed with the first external terminal of the amplifier circuit unit.
Programmable baseband filter for selectively coupling with at least a portion of another filter
An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.
INTEGRATED MIXED-SIGNAL ASIC WITH ADC, DAC, AND DSP
An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
DIGITAL TRANSMITTER FEATURING A 50%-LO SIGNED PHASE MAPPER
Digitally controlled segmented RF power transmitter with a digital processing part (2) and an RF power amplification part (3) having a plurality of segments (122). The digital processing part (2) has a clock generation block (5) being arranged to generate n equi-phased clock signals with a 50% duty-cycle (f.sub.LO,x_50%; C.sub.x), and a sign-bit phase mapper unit (11) being arranged to receive the n equi-phased clock signals (f.sub.LO,x_50%; C.sub.x), and sign signals (Sign.sub.I, Sign.sub.Q; sign bits), and to output a set of m, m?n, phase mapped clock signals with a 50% duty-cycle (CLK.sub.y,50%; C.sub.y) using a predetermined phase swapping scheme. Each of the plurality of segments (122) comprises logic circuitry (12) receiving the set of m phase-mapped clock signals with a 50% duty-cycle (CLK.sub.y,50%; C.sub.y), and being arranged to provide the respective segment driving signal with a duty-cycle z of less than 50%.
Dynamic frequency correction in delta-sigma based software defined receiver
A method and apparatus for dynamically modifying filter characteristics of a Delta-Sigma modulator to accommodate for Doppler shift. A transceiver in a wireless cellular communication system for adapt to changes in the RF carrier frequency for maintaining signal integrity by applying a pilot tone in calibration to determine a frequency shift response for a bandpass filter. During operation, the system is operative to determine a Doppler shift and to shift the bandpass filter in response.
Transformation based filter for interpolation or decimation
A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.