In a signal detection apparatus, a quadrature detection circuit subjects a reception signal to quadrature detection. An intensity detection circuit detects a signal intensity by referring to an absolute value of an amplitude of a signal subjected to quadrature detection. A zero cross detection circuit detects the number of times of zero crosses of the signal in a predetermined period of time that is based on a modulation index of the reception signal. A signal determination circuit that determines that the signal is the reception signal when the signal intensity is equal to or higher than a threshold value and the number of times of zero crosses is within a predetermined range.

A device for processing a received signal by a receiver disrupted by a transmitter, wherein the transmitters and receiver are co-located, includes: a first coupler configured to take a first reference signal; an analogue circuit for processing the first reference signal; a second coupler configured to combine the modified reference signal with the signal received by an antenna of the receiver; a first analogue-to-digital conversion module digitising the first reference signal; the second analogue conversion module digitising the combined signal in order to deliver a digital combined signal to the digital signal-processing device, wherein signal-processing device delivers a resulting digital signal to a data-processing module of the receiver device.

A device for processing a received signal by a receiver disrupted by a transmitter, wherein the transmitters and receiver are co-located, includes: a first coupler configured to take a first reference signal; an analogue circuit for processing the first reference signal; a second coupler configured to combine the modified reference signal with the signal received by an antenna of the receiver; a first analogue-to-digital conversion module digitising the first reference signal; the second analogue conversion module digitising the combined signal in order to deliver a digital combined signal to the digital signal-processing device, wherein signal-processing device delivers a resulting digital signal to a data-processing module of the receiver device.

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

A delay circuit for time offsetting an input radiofrequency signal, includes an all-pass filter having a given central frequency to linearize a phase-shift of an output signal relative to the input signal as a function of the frequency on a first frequency range; and first and second antiresonant circuits having respectively first and second central frequencies, the all-pass filter and the antiresonant circuits configured to linearize the phase-shift of the output signal relative to the input signal as a function of the frequency on a second frequency range including the first range. The difference between first and second central frequencies is less than 30% of the value of one of both frequencies, the difference between the first central frequency and the given central frequency of the all-pass filter is less than 30% of the value of a highest frequency between the first central frequency and the given central frequency.

Disclosed is a method and apparatus for phase error compensation having tolerance to a cyclic slip. The method includes determining first phase error candidates based on symbol phases of a first block of a received signal, determining an initial estimation error according to the first phase error candidates, determining second phase error candidates based on symbol phases of a second block of the received signal, determining a final estimation error according to the initial estimation error and the second phase error candidates, and compensating for a phase of the received signal according to the final estimation error.

Disclosed is a method and apparatus for phase error compensation having tolerance to a cyclic slip. The method includes determining first phase error candidates based on symbol phases of a first block of a received signal, determining an initial estimation error according to the first phase error candidates, determining second phase error candidates based on symbol phases of a second block of the received signal, determining a final estimation error according to the initial estimation error and the second phase error candidates, and compensating for a phase of the received signal according to the final estimation error.

A cascadable AGC amplifier in a signal distribution system includes a low noise cascadable amplifier having a through path and a cascadable output. The cascadable amplifier is also configured to provide AGC over a predetermined input power range. The cascadable AGC amplifier can be configured to provide gain or attenuation. When the cascadable AGC amplifier is implemented in a signal distribution system, typically as part of a signal distribution device, an input signal can be gain controlled and supplied to multiple signal paths without distortion due to degradation of signal to noise ratio or distortion due to higher order amplifier products. The distributed signal is not significantly degraded by distortion regardless of the number of cascadable AGC amplifiers connected in series or the position of the cascadable AGC amplifier in the signal distribution system.

Described are concepts, systems, devices and methods that enhance decoding performance of channels subject to correlated noise. The concepts, systems, devices and methods can be used with any combination of codes, code-rates and decoding techniques. In embodiments, a continuous realization of effective noise is estimated from a lead channel by subtracting its decoded output from its received signal. This estimate is then used to improve the accuracy of decoding of an otherwise orthogonal channel that is experiencing correlated effective noise. In this approach, channels aid each other through the post-decoding provision of estimates of effective noise. In some embodiments, the lead channel is not pre-determined, but is chosen dynamically based on which of a plurality of decoders completes first, or using soft information including an estimate of effective noise that is least energetic or most likely to have occurred.

Methods and systems for a passive noise dampener. A system includes a hybrid fiber-coaxial network which carries content signals between a service provider system and premises, where the hybrid fiber-coaxial network is susceptible to receiving wireless noise signals, a plurality of passive noise dampeners, each passive noise dampener connected between the hybrid fiber-coaxial network and a premise of the premises. Each passive noise dampener includes an antenna based on medium used in the hybrid fiber-coaxial network. The antenna receives the wireless noise signals. A phase shifting device phase shifts 180 degrees phase shift the wireless noise signals received by the antenna to generate a counter signal. A directional coupler injects the counter signal into the hybrid fiber-coaxial network to mitigate impact of the wireless noise signals received by the hybrid fiber-coaxial network on the content signals. The antenna, the phase shifting device, and the directional coupler are passive devices.