A front-end module may include an acoustic wave filter with a first and second interdigital transducer electrode. The first interdigital transducer electrode may be single-ended with a first input bus bar that receives an input signal and a second input bus bar connected to ground. The second interdigital transducer electrode may be differential with a first output bus bar connected to a first output terminal and a second output bus bar connected to a second output terminal. The front-end module may include a low noise amplifier (LNA) that outputs a differential signal via a differential output and has a differential input connected to the acoustic wave filter. The LNA may include a first input transistor that receives a first signal from the first output terminal of the acoustic wave filter and a second input transistor that receives a second signal from the second output terminal of the acoustic wave filter.

According to one embodiment, an electronic apparatus includes a receiver and a signal addition circuit. The receiver receives a reception signal of a first frequency band. The signal addition circuit is configured to input the reception signal and a calibration signal of a second frequency band which is different from the first frequency band to the receiver.

According to one embodiment, an electronic apparatus includes a receiver and a signal addition circuit. The receiver receives a reception signal of a first frequency band. The signal addition circuit is configured to input the reception signal and a calibration signal of a second frequency band which is different from the first frequency band to the receiver.

A data processing unit creates a database for electric field levels of predetermined frequency bands received by a second tuner. An interfering station determination unit determines whether or not there are a first interfering station and a second interfering station to generate intermodulation interference of third-order distortion with respect to a specific receiving station. A gain calculation unit calculates, as a gain attenuation amount, a difference between at least one of an electric field level of the first interfering station and an electric field level of the second interfering station that are included in the database created by the data processing unit and a reference electric field level at which no intermodulation interference of third-order distortion occurs, the reference electric field level set on the basis of output saturation characteristics of a first high-frequency amplifier inside a first tuner, in a case where the interfering station determination unit determines that there are the first interfering station and the second interfering station. A gain control unit controls the gain of the first high-frequency amplifier using the gain attenuation amount.

Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

A signal processor and method of signal processing for a radio receiver is described. An input signal is received together with a spectral repetition interval value of an interferer signal. An interference reference signal is generated from the received spectral repetition interval value and the received signal. The received signal is adapted using the generated interference reference signal.

A signal processor and method of signal processing for a radio receiver is described. An input signal is received together with a spectral repetition interval value of an interferer signal. An interference reference signal is generated from the received spectral repetition interval value and the received signal. The received signal is adapted using the generated interference reference signal.

A transmitter circuit includes at least one transmitting signal processing device, a compensation device and a compensation value calibration device. The compensation device generates a first compensated input signal and a second compensated input signal by respectively processing input signals according to a first compensation value and a second compensation value. The transmitting signal processing device generates a first output signal and a second output signal by processing the first compensated input signal and the second compensated input signal. The compensation value calibration device receives the first output signal and the second output signal as a first feedback signal and a second feedback signal, respectively, and includes a digital signal processor. The digital signal processor determines a calibrated compensation value according to power of the first feedback signal and the second feedback signal at a predetermined frequency and the first compensation value and the second compensation value.

A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.