A pseudo low intermediate frequency (IF) configuration is provided for a receiver having a zero IF radio architecture dedicated for radar detection, in order to reduce false radar detection. Energy from local oscillator leakage is shifted away from DC. After filtering out of the desired sub-channel, the local oscillator leakage energy is suppressed, reducing false radar detection.

In a receiver that demodulates a received signal, deterioration of signal quality is suppressed. A current output unit generates and outputs, from a voltage signal, a current signal including a predetermined offset current in a low-frequency component between a high-frequency component having a frequency higher than a predetermined frequency and the low-frequency component having a frequency lower than the predetermined frequency. A demodulation unit demodulates the high-frequency component. A filter circuit passes, in the current signal, the high-frequency component from a current output unit to the demodulation unit, and causes the low-frequency component to flow from the current output unit to a predetermined reference potential point.

In a receiver that demodulates a received signal, deterioration of signal quality is suppressed. A current output unit generates and outputs, from a voltage signal, a current signal including a predetermined offset current in a low-frequency component between a high-frequency component having a frequency higher than a predetermined frequency and the low-frequency component having a frequency lower than the predetermined frequency. A demodulation unit demodulates the high-frequency component. A filter circuit passes, in the current signal, the high-frequency component from a current output unit to the demodulation unit, and causes the low-frequency component to flow from the current output unit to a predetermined reference potential point.

The present disclosure provides a signal calibration method, apparatus and device generated based on an imbalance of I path and Q path. The method includes sending a cosine signal and a sine signal through a signal generator, transmitting the cosine signal and the sine signal in the I path and the Q path respectively, the cosine signal and the sine signal being configured to loop back to a signal receiving direction after passing through a transmitting amplifier; processing a signal obtained by a down converter in the signal receiving direction; performing a phase adjustment and an amplitude adjustment by adjusting the signal generator, gain amplifiers of I path and Q path analog domains, and a corresponding digital domain, so as to determine an appropriate phase cancellation value and an appropriate amplitude cancellation value for an image signal; and calibrating the image signal corresponding to the signal to be calibrated.

An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.

A family of radio frequency (RF) filter circuits that use radio frequency linear mixers to controllably separate desired frequency spectrum from undesired frequency spectrum, and convert signals from one frequency to another, permitting inclusion in a closed- or open-loop control circuit that supports rapid dynamic manipulation of the filter circuit's center frequency and bandwidth.

A family of radio frequency (RF) filter circuits that use radio frequency linear mixers to controllably separate desired frequency spectrum from undesired frequency spectrum, and convert signals from one frequency to another, permitting inclusion in a closed- or open-loop control circuit that supports rapid dynamic manipulation of the filter circuit's center frequency and bandwidth.

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

Circuits for a receiver, comprising: M first mixers that each receive an input signal, that are each clocked by a different phase of a first common clock frequency, and that each provide an output, wherein M is a count of the first mixers; and M sets of N second mixers, wherein N is a count of the second mixers in each of the M sets, wherein each second mixer in each set of N second mixers receives as an input the output of a corresponding one of the M first mixers, wherein each of the N second mixers in each of the M sets are clocked by a different phase of a second common clock frequency, and wherein each of the second mixers has an output.

The disclosure relates to a four-port diplexer device which includes a first port configured to pass signals within a first frequency band and to block signals within a second frequency band; a second port configured to pass signals within the second frequency band and to block signals within the first frequency band; a third port configured to transmit a first signal portion of a combination of the signals received from the first port and the signals received from the second port; and a fourth port configured to transmit a second signal portion of the combination of the signals received from the first port and the signals received from the second port.