Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

The disclosed embodiments relate to the design of an equalizer that uses both cross-coupled cascodes and inductive peaking to reduce distortion in a signal received from a communication channel by attenuating lower frequencies and amplifying higher frequencies. At lower frequencies, when the effects of inductive impedance within the equalizer are negligible, the equalizer essentially functions as a traditional cascode amplifier that presents high gain. At higher frequencies, the increases in inductive impedances within the equalizer act to boost a gain of the equalizer.

A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

A analog equalizer includes: an adjusting circuit, generating an adjustment signal and a selection signal; a cascaded equalization circuit, receiving the adjustment signal, and adjusting at least one of a tunable resistor, a tunable capacitor and a tunable current source in the multi-stage equalization circuit according to the adjustment signal to perform an equalization process on a signal to be equalized; and an analog multiplexer, coupled to the cascaded equalization circuit and the adjusting circuit, selecting and outputting an equalized signal outputted from one stage of the multi-stage equalization circuit according to the selection signal. Wherein, the adjusting circuit adjusts the adjustment signal and the selection signal according to the equalized signal outputted from the analog multiplexer and a target equalization value.

A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

A distortion compensation system includes a first communication node including a first reception unit including an equalizer configured by a first digital filter unit and a first transmission unit including an emphasis circuit configured by a second digital filter unit, and a second communication node including a second transmission unit transmitting a training pattern before receiving normal data from the first communication node. The equalizer converges a filter constant of the first digital filter unit so that an error of the received training pattern is converged. The first transmission unit performs a distortion compensation using the converged filter constant of the first digital filter unit as at least a part of a filter constant of the second digital filter unit of the emphasis circuit, and then transmits the data.

A semiconductor device and a serial data transmission line system have a reception circuit and an adaptive equalizer circuit. A supply source of a power supply supplied with the reception circuit is selected based on correction intensity of the correction value calculated by the adaptive equalizer circuit. When correction intensity of the correction value calculated by the adaptive equalizer circuit is not less than a threshold value, the supply source of the power supply supplied to the reception circuit and the adaptive equalizer circuit is switched, and a noise level of the power supply is reduced.

An information handling system may include a plurality of communication destinations, a communication source, a single-source/multi-destination cable having a plurality of branches, each branch communicatively coupling the communication source to a communication destination respective to such branch, and a logic device communicatively coupled to the communication source and the single-source/multi-destination cable and configured to communicate to each of the plurality of branches both analog source identifying information and digital source identifying information regarding the communication source.

A physical layer transceiver, for connecting a host device to a wireline channel medium that is divided into a total number of link segments, includes a host interface for coupling to a host device, a line interface for coupling to the wireline channel medium, and feed-forward equalization (FFE) circuitry operatively coupled to the line interface to add back, into a signal, components that were scattered in time. Respective individual filter segments are selectably configurable, by adjustment of respective delay lines, to correspond to respective individual link segments. The FFE circuitry also includes control circuitry configured to detect a signal energy peak in at least one particular link segment and, upon detection of the signal energy peak in the particular link segment, configure a respective one of the respective individual filter segments, by adjustment of a respective delay line, to correspond to the respective particular link segment.