H04B3/493

Ethernet Transceiver with PHY-Level Signal-Loss Detector
20200106594 · 2020-04-02 ·

An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal.

Ethernet transceiver with PHY-level signal-loss detector
10530559 · 2020-01-07 · ·

An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal.

Ethernet transceiver with PHY-level signal-loss detector
10530559 · 2020-01-07 · ·

An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal.

Full-duplex echo cancellation

Facilitating echo cancellation within communication networks is contemplated, such as but not necessarily limited to facilitating echo cancellation within full-duplex (FDX) communication networks. The echo cancellation may optionally be performed with an echo canceller included as part of or otherwise associated with an FDX node used to facilitate interfacing signaling between a digital domain and an analog domain of a FDX or other communication network.

Method and apparatus for monitoring a communication line

Embodiments relate to an apparatus comprising means configured for: obtaining echo response data representative of the echo response of a communication line, wherein the echo response data specifies the echo response based on two dimensions and includes first dimension data and second dimension data, determining at least one property of the communication line based on processing the echo response data with a neural network, wherein the neural network comprises at least: a first convolutional branch for processing the first dimension data, a second convolutional branch for processing the second dimension data, a dense part for processing the outputs of the first and second convolutional branches.

Method and apparatus for monitoring a communication line

Embodiments relate to an apparatus comprising means configured for: obtaining echo response data representative of the echo response of a communication line, wherein the echo response data specifies the echo response based on two dimensions and includes first dimension data and second dimension data, determining at least one property of the communication line based on processing the echo response data with a neural network, wherein the neural network comprises at least: a first convolutional branch for processing the first dimension data, a second convolutional branch for processing the second dimension data, a dense part for processing the outputs of the first and second convolutional branches.

Global resistor calibration for transceivers

Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor. Various programmable resistors within a calibration control loop may, for example, substantially improve termination impedances of high-speed transmission lines and may mitigate random resistive mismatch variations.

Global resistor calibration for transceivers

Apparatus and associated methods relate to a programmable resistor having a resistance iteratively programmed by a calibration control loop. In an illustrative example, the calibration control loop may alternately sample the programmable resistance and a reference resistance by producing a corresponding voltage drop across the resistors. The voltage drops may, for example, be induced by the same constant current source. The calibration control loop may compare the voltage drops with a comparator, for example. In some examples, the comparator may provide a count direction signal to a logic block, generating a calibration code. The calibration code may, for example, be applied to the programmable resistor, such that the resistance of the programmable resistor iteratively approaches the resistance of the reference resistor. Various programmable resistors within a calibration control loop may, for example, substantially improve termination impedances of high-speed transmission lines and may mitigate random resistive mismatch variations.

SMART AMPLIFIER DIAGNOSTIC SYSTEMS AND METHODS
20240162934 · 2024-05-16 ·

An amplifier for a cable network includes circuitry configured to provide a diagnostic parameter. Exemplary parameter include one or more of: measurements of a frequency response, suckouts in the frequency domain, north upstream echo signal or power, north downstream signal or power, north upstream echo to downstream power ratio, north upstream echo to residual echo power ratio, downstream echo canceller coefficients, south downstream signal or power, upstream information, south downstream echo signal or power, south upstream signal or power, south downstream echo to upstream power ratio, south downstream echo to residual echo power ratio, upstream echo canceller coefficients, and north upstream signal or power.

SMART AMPLIFIER DIAGNOSTIC SYSTEMS AND METHODS
20240162934 · 2024-05-16 ·

An amplifier for a cable network includes circuitry configured to provide a diagnostic parameter. Exemplary parameter include one or more of: measurements of a frequency response, suckouts in the frequency domain, north upstream echo signal or power, north downstream signal or power, north upstream echo to downstream power ratio, north upstream echo to residual echo power ratio, downstream echo canceller coefficients, south downstream signal or power, upstream information, south downstream echo signal or power, south upstream signal or power, south downstream echo to upstream power ratio, south downstream echo to residual echo power ratio, upstream echo canceller coefficients, and north upstream signal or power.