The present technology relates to a transmission apparatus, a transmission method, and a filter circuit that make it possible to transmit a signal with high quality, the signal including a plurality of signals having different speeds. The transmission apparatus includes a detection unit that detects each of a plurality of signals having different speeds from an input signal. Further, the transmission apparatus includes an output control unit that controls output of an output signal including the plurality of signals, on the basis of detection results of the plurality of signals by the detection unit. The present technology can be applied to, for example, a transmission apparatus that transmits a serial signal conforming to the USB 3.0 standards or a transmission apparatus that converts the serial signal described above into a millimeter-wave signal or an optical signal and sends and receives the signal.

A connector device includes a pluggable interface and a corresponding connector. The pluggable interface includes multiple rows of pads. Similarly, the connector includes multiple rows of contacts to contact the multiple rows of pads. The multiple rows of pads can further be subdivided where at least certain pad locations are subdivided into two smaller pads. At least certain pads can be disposed at angles other than right angles. The connector can include a cover with a mechanism to depress the second row of contacts. The depression mechanism is engaged via side wings on the cover engage with legacy plugs and avoid contact between the second row of contacts and the pads of the legacy plug.

A connector device includes a pluggable interface and a corresponding connector. The pluggable interface includes multiple rows of pads. Similarly, the connector includes multiple rows of contacts to contact the multiple rows of pads. The multiple rows of pads can further be subdivided where at least certain pad locations are subdivided into two smaller pads. At least certain pads can be disposed at angles other than right angles. The connector can include a cover with a mechanism to depress the second row of contacts. The depression mechanism is engaged via side wings on the cover engage with legacy plugs and avoid contact between the second row of contacts and the pads of the legacy plug.

A data carrier 2 is provided with a comparator 41, a capacitor 42, a comparator operation adjustment resistor 43, a resistance voltage divider circuit 44 and a reactive-current resistor 45. The capacitor 42 is disposed between the cathode of a photo-diode (PD) 21 and the minus input terminal of the comparator 41. The comparator operation adjustment resistor 43 is disposed between the plus terminal of a primary battery 271 and the minus input terminal of the comparator 41. The resistance voltage divider circuit 44 is constituted by a series connection of voltage dividing resistors 441 and 442. One end of the resistance voltage divider circuit 44 is connected to the plus terminal of the primary battery 271. The junction between the voltage division resistor 441 and the other voltage division resistor 442 is connected to the plus input terminal of the comparator 41.

A data carrier 2 is provided with a comparator 41, a capacitor 42, a comparator operation adjustment resistor 43, a resistance voltage divider circuit 44 and a reactive-current resistor 45. The capacitor 42 is disposed between the cathode of a photo-diode (PD) 21 and the minus input terminal of the comparator 41. The comparator operation adjustment resistor 43 is disposed between the plus terminal of a primary battery 271 and the minus input terminal of the comparator 41. The resistance voltage divider circuit 44 is constituted by a series connection of voltage dividing resistors 441 and 442. One end of the resistance voltage divider circuit 44 is connected to the plus terminal of the primary battery 271. The junction between the voltage division resistor 441 and the other voltage division resistor 442 is connected to the plus input terminal of the comparator 41.

A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.

An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

A first device receives a first container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames, each of which includes an optical data unit (ODU) frame and a sequence of forward error correction (FEC) bits for the ODU frame. Each OTU frame is associated with a first sequence of error-identifying bits. The first device determines, for each OTU frame, a second sequence of error-identifying bits, and forms a second container frame including the OTU frames, the first sequences of error-identifying bits, and the second sequences of error-identifying bits. The first device transmits the second container frame to a second device.

A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.