H04B10/802

Distributed traveling-wave photodetector
20250247158 · 2025-07-31 ·

An optical communication receiver includes an optical input configured to receive from a communication link a modulated optical wave conveying data over the communication link, and a multimode waveguide, which is coupled to receive the modulated optical wave from the optical input and has a width that is selected to cause the modulated optical wave to form multiple interference maxima over an area of the multimode waveguide. The optical communication receiver further includes multiple optical detectors disposed over the multimode waveguide in alignment with respective ones of the interference maxima and configured to output electrical signals in response to optical energy absorbed by the optical detectors from the multimode waveguide, and signal processing circuitry coupled to process and demodulate the electrical signals so as to extract and output the data.

ON-BOARD OPTICAL CONNECTION DEVICE
20250244533 · 2025-07-31 ·

An on-board optical connection device, connected between a first data processing device and a second data processing device, includes an optical waveguide, a first signal transceiver, and a second signal transceiver. The optical waveguide is disposed between the first data processing device and the second data processing device. The first signal transceiver is optically coupled to the optical waveguide and converts an input electrical signal transmitted from the first data processing device to an optical signal. The second signal transceiver is optically coupled to the optical waveguide and converts the optical signal to an output electrical signal to the second data processing device.

Electromagnetic interference suppression circuit and intelligent electronic device

Provided in the embodiments are an electromagnetic interference suppression circuit and an intelligent electronic device. The electromagnetic interference suppression circuit comprises at least one ferrite bead located at the input port of the circuit, a transient voltage suppression diode, wherein either terminal of the transient voltage suppression diode is connected with the at least one ferrite bead, a resistor network connected with the transient voltage suppression diode, and an optocoupler with an alternating current input response coupled to resistor network.

REALLOCATION OF RESOURCES FOR ISOLATING OPTICAL COMMUNICATIONS

Examples described herein relate to circuitry coupled to a memory configured to: report telemetry data indicative of access to a first region of the memory; and based on a first command, selectively adjust resources of the memory allocated to communications between a first process and a second process. In some examples, the first region of the memory is accessible to the first process and the second process via optical interconnects. In some examples, the resources of the memory comprise one or more of: a number of addresses in a memory region, a set of memory addresses, or memory bandwidth.

OPTICAL SPLITTER COMPONENT
20250350371 · 2025-11-13 ·

An apparatus is provided. The apparatus includes a first connector configured to interface with a 200 gigabit (200G) optical transceiver. The apparatus also includes a second connector coupled to the first connector via a first set of optical fibers. The apparatus further includes a splitter portion. The splitter portion includes a third connector communicatively coupled to the second connector. The splitter portion also includes a fourth connector coupled to the third connector via a second set of optical fibers and a fifth connector coupled to the third connecter via a third set of optical fibers.

OPTICAL SWITCH TO ISOLATE DATA ACCESSES IN MEMORY

Examples described herein relate to a first circuitry, wherein the first circuitry comprises one or more of: a first memory, a first processor, or a first accelerator; a second circuitry, wherein the first circuitry and the second circuitry are communicatively coupled by optical interfaces and wherein the second circuitry comprises one or more of: a second memory, a second processor, or a second accelerator; and a switch configured to provide optical and/or electrical signal isolation between the first and second circuitries based on a configuration. In some examples, the configuration is to specify whether optical, electrical, or optical and electrical communications are permitted and an access level.

Power status telemetry for powered devices in a system with power over ethernet

A powered device interface assembly includes an optocoupler and a powered device interface. The opto-coupler is electrically coupled with a microcontroller of the power device interface. The powered device interface includes a telemetry circuit coupled with the opto-coupler and configured to generate encoded telemetry information for output via a single pin of the powered device interface for transmission to the microcontroller of the powered device, wherein the opto-coupler is coupled with the single pin and is configured to electrically isolate the single pin from the microcontroller.

Pulse oximetry system with electrical decoupling circuitry

A pulse oximetry system for reducing the risk of electric shock to a medical patient can include physiological sensors, at least one of which has a light emitter that can impinge light on body tissue of a living patient and a detector responsive to the light after attenuation by the body tissue. The detector can generate a signal indicative of a physiological characteristic of the living patient. The pulse oximetry system may also include a splitter cable that can connect the physiological sensors to a physiological monitor. The splitter cable may have a plurality of cable sections each including one or more electrical conductors that can interface with one of the physiological sensors. One or more decoupling circuits may be disposed in the splitter cable, which can be in communication with selected ones of the electrical conductors. The one or more decoupling circuits can electrically decouple the physiological sensors.

PHOTON ARCHITECTURE FOR BI-DIRECTIONAL AND CO-DIRECTIONAL LINKS
20260088913 · 2026-03-26 ·

A photonic circuit and/or chip is provided that is configured for selective use in a bi-directional link or a co-directional link. The photonic circuit and/or chip includes a coupling waveguide; receiver filters that are each a tunable bandpass filter; and two or more wavelength branches. Each wavelength branch corresponds to a respective wavelength and includes a receiver arm comprising a signal detection component and a transmitter arm comprising a signal generator configured to provide a transmission signal to the coupling waveguide. The receiver arm is in optical communication with the coupling waveguide via a receiver filter. When the receiver filter is tuned to pass the respective wavelength, the wavelength branch corresponding to the respective wavelength is configured to act as a receiver. When the receiver filter is tuned to not pass the respective wavelength, the wavelength branch corresponding to the respective wavelength is configured to not act as a receiver.

DISAGGREGATED MEMORY STRUCTURES ON A DIRECTLY MODULATED PHOTONIC WAFER-SCALE INTERPOSER

Circuits, such as chiplets and memory devices, and surface-emitting light sources, such as vertical-cavity surface-emitting lasers (VCSELs), are bonded to a front side of a photonic wafer-scale interposer (PWSI). The PWSI includes waveguides for communication among the circuits, memory devices, and surface-emitting light sources. Memory devices are grouped by a memory fabric, resulting in a disaggregated memory structure. A first circuit accesses memory. The accessing is based on the disaggregated memory structure. The accessing can include sending electrical data by the first circuit to a first surface-emitting light source. A degree of freedom (DoF) of a light beam emitted by the first surface-emitting light source can be modulated. The emitted light beam can comprise a degree of freedom modulated beam (DFMB) that is based on the sent electrical data. The memory fabric can allocate memory based on memory needs of the first circuit.