The present disclosure provides apparatuses, systems, methods, and machine readable storage medium for physical uplink shared channel (PUSCH) transmission between a user equipment (UE) and a base station, based on a robust codebook. In an embodiment, a UE, including circuitry operable to: report a UE capability of the UE to a base station, wherein the UE capability comprises a number of phase tracking reference signal (PT-RS) antenna ports (N.sub.PT-RS) supported by the UE; decode control signaling received from the base station, wherein the control signaling comprises at least one parameter to indicate a precoder selected from a codebook based on at least the N.sub.PT-RS; and perform physical uplink shared channel (PUSCH) transmission according to the indicated precoder; wherein the codebook is predefined or configured based on different numbers of PT-RS antenna ports and different waveforms, in the UE and the base station.

Methods and systems are disclosed for concurrent transmission or resource blocks allocated to a mobile device for transmission in uplink communication channels. In particular implementations, a mobile device may tune local oscillators and/or apply filtering of radio frequency transmission to reduce or mitigate intermodulation distortion potentially affecting one or more radio frequency receiving functions.

Methods and systems are disclosed for concurrent transmission or resource blocks allocated to a mobile device for transmission in uplink communication channels. In particular implementations, a mobile device may tune local oscillators and/or apply filtering of radio frequency transmission to reduce or mitigate intermodulation distortion potentially affecting one or more radio frequency receiving functions.

An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.

An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.

A digital predistortion (DPD) verification and transmitter nonlinearity estimation system includes a transmitter path including one or more power amplifiers (PAs) coupled to an upconversion mixer. A digital tone generator circuit generates a single-tone radio-frequency (RF) signal that is applied to a first input of the upconversion mixer to generate a dual-tone RF signal, where a second input of the upconversion mixer is disabled. A downconversion mixer downconverts an amplified dual-tone RF signal to generate an intermediate-frequency (IF) dual-tone signal. A processing block analyzes the IF dual-tone signal to estimate signal strengths of one or more intermodulation (IM) product signals.

A digital predistortion (DPD) verification and transmitter nonlinearity estimation system includes a transmitter path including one or more power amplifiers (PAs) coupled to an upconversion mixer. A digital tone generator circuit generates a single-tone radio-frequency (RF) signal that is applied to a first input of the upconversion mixer to generate a dual-tone RF signal, where a second input of the upconversion mixer is disabled. A downconversion mixer downconverts an amplified dual-tone RF signal to generate an intermediate-frequency (IF) dual-tone signal. A processing block analyzes the IF dual-tone signal to estimate signal strengths of one or more intermodulation (IM) product signals.

A mixer circuitry comprises a mixer, a local oscillator (LO) leakage detector, a digital LO leakage cancellation controller and a DAC arrangement. The mixer is configured to mix a first LO signal having an LO frequency f.sub.LO with an intermediate frequency (IF) signal and generate an output signal, i.e. a wanted signal. The LO leakage detector measures the LO leakage at the output of the mixer in the presence of the wanted signal. Then in the digital LO leakage cancellation controller, a digital algorithm is run that automatically adjusts the LO leakage in the mixer by steering the digital-to-analog converter arrangement such that the intermediate frequency input signal level to the mixer is adjusted.

A mixer circuitry comprises a mixer, a local oscillator (LO) leakage detector, a digital LO leakage cancellation controller and a DAC arrangement. The mixer is configured to mix a first LO signal having an LO frequency f.sub.LO with an intermediate frequency (IF) signal and generate an output signal, i.e. a wanted signal. The LO leakage detector measures the LO leakage at the output of the mixer in the presence of the wanted signal. Then in the digital LO leakage cancellation controller, a digital algorithm is run that automatically adjusts the LO leakage in the mixer by steering the digital-to-analog converter arrangement such that the intermediate frequency input signal level to the mixer is adjusted.

An integrated circuit is disclosed. The integrated circuit includes a set of transceivers comprising a plurality of transceivers, all configured to transmit in the same transmit frequency band and receive in the same receive frequency band. Furthermore, the integrated circuit has a set of frequency synthesizers including a separate frequency synthesizer associated with each transceiver in the set of transceivers, wherein each frequency synthesizer in the set is configured to generate a local-oscillator (LO) signal to its associated transceiver. Moreover, the integrated circuit includes a control circuit configured to control the set of frequency synthesizers such that nearest neighbors in the set of frequency synthesizers generate LO signals at different frequencies (f.sub.1, f.sub.2, f.sub.3, f.sub.4).