Patent classifications
H04B2201/7073
Time to digital converter and phase locked loop
A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.
Wide area positioning system
Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.
TIME SYNCHRONIZATION FOR WIRELESS DEVICE
A method for time synchronization for wireless device. The method comprises receiving a modulated signal from a second wireless device, the modulated signal indicating information of a first PPS signal for time synchronization, and the first PPS signal being received by the second wireless device via a network protocol for time synchronization or a GNSS receiver. The method further comprises obtaining a second PPS signal by demodulating the received modulated signal. The method further comprises determining a delay offset between the first PPS signal and the second PPS signal. Furthermore, the method further comprises recovering the first PPS signal for time synchronization based on the second PPS signal and the delay offset. In this manner, the accuracy of the time synchronization can be improved, and the cost for the entire network can be reduced.
Bidirectional data communication system, in particular exploiting a CDMA coding and two unidirectional data buses
Communication system, comprising: a first data bus configured to transport a first data signal according to a first transmission direction; a second data bus configured to transport a second data signal according to a second transmission direction different from the first transmission direction; a synchronization bus; and a plurality of local resources generating a respective local signal to be transmitted on the first and second data bus. All transceivers are modulated with CDMA encoding and take place following a synchronism signal. The unidirectionality of transmission on the data buses guarantees the absence of interference. The communication system is fully scalable.
Clock and data recovery circuit with spread spectrum clocking synthesizer
The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR includes a phase detector, a digital loop filter, a first phase interpolator and a second phase interpolator. The PLL is configured to generate a first clock signal with SSC modulation and a control signal. The phase detector is configured to generate a detection result according an input signal and an output clock signal, wherein the input signal is with SSC modulation. The digital loop filter is configured to filter the detection result to generate a filtered signal. The first phase interpolator is configured to generate a second clock signal according to the filtered signal and the first clock signal. The second phase interpolator is configured to cancel an SSC component contributed by the first clock signal in the second clock signal to generate the output clock signal according to the control signal.
Time synchronization for wireless device
A method for time synchronization for wireless device. The method comprises receiving a modulated signal from a second wireless device, the modulated signal indicating information of a first PPS signal for time synchronization, and the first PPS signal being received by the second wireless device via a network protocol for time synchronization or a GNSS receiver. The method further comprises obtaining a second PPS signal by demodulating the received modulated signal. The method further comprises determining a delay offset between the first PPS signal and the second PPS signal. Furthermore, the method further comprises recovering the first PPS signal for time synchronization based on the second PPS signal and the delay offset. In this manner, the accuracy of the time synchronization can be improved, and the cost for the entire network can be reduced.