Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A Global Navigation Satellite System (GNSS) receiver demodulates code shift keying (CSK) data utilizing a binary search. The GNSS receiver receives a signal including a pseudorandom noise (PRN) code modulated by code shift keying (CSK) to represent a symbol (i.e., CSK modulated symbol). The GNSS receiver maintains a plurality of receiver codes each representing a different shift in chips to the PRN code. The GNSS receiver performs a linear combination of portions of the receiver codes. In an embodiment, the GNSS receiver compares correlation power level value for respective portions of the receiver codes to demodulate the CSK data. In a further embodiment, the GNSS receiver compares the correlation power level values for portions of receiver codes with power detection threshold values to demodulate the CSK data. In a further embodiment, the GNSS receiver utilizes signs of the correlation power level values to demodulate the CSK data.

An RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. In addition, a clock system can include an RF clocked device. The RF clocked device can include a signal processor operable to receive an RF signal having an RF signal frequency and output a clock signal having a clock frequency based on the RF signal frequency. The RF clocked device can also include a clock operable to receive, and operate, using the clock signal. The clock can output at least one of a time and a date. The clock system can also include a client device operable to receive timing information from the RF clocked device.

System and method for processing an analog signal. For example, a demodulator for processing an analog signal includes one or more analog-to-digital converters configured to receive an analog signal and generate a digital signal based at least in part on the analog signal, and a correlator coupled to the one or more analog-to-digital converters and configured to generate a stream of correlation results including a first plurality of correlation results, a second plurality of correlation results, and a third plurality of correlation results. The first plurality of correlation results is different from the second plurality of correlation results by at least one correlation result, and the second plurality of correlation results is different from the third plurality of correlation results by at least another correlation result.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Disclosed are a spread-spectrum decoding method for a transmitted signal and a display apparatus. The method comprises: acquiring a fixed input frequency of an input signal, and taking the fixed input frequency as a decoding frequency; performing a calculation according to the fixed input frequency to obtain a cycle number N of the input signal within a pre-set time range; determining whether, during the pre-set time range, the ratio of the number of cycles corresponding to the input frequency after the spread-spectrum processing, which is greater than or less than the decoding frequency, to the cycle number N is greater than or equal to a pre-set percentage; if so, adding a one stage pre-set adjustment frequency value to the decoding frequency or subtracting same from the decoding frequency so as to obtain a new decoding frequency; and taking the new decoding frequency as an updated decoding frequency.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

A Global Navigation Satellite System (GNSS) receiver demodulates code shift keying (CSK) data utilizing a binary search. The GNSS receiver receives a signal including a pseudorandom noise (PRN) code modulated by code shift keying (CSK) to represent a symbol (i.e., CSK modulated symbol). The GNSS receiver maintains a plurality of receiver codes each representing a different shift in chips to the PRN code. The GNSS receiver performs a linear combination of portions of the receiver codes. In an embodiment, the GNSS receiver compares correlation power level value for respective portions of the receiver codes to demodulate the CSK data. In a further embodiment, the GNSS receiver compares the correlation power level values for portions of receiver codes with power detection threshold values to demodulate the CSK data. In a further embodiment, the GNSS receiver utilizes signs of the correlation power level values to demodulate the CSK data.

An aspect of the present disclosure includes methods, systems, and computer-readable media for receiving a first timing reference signal and a second timing reference signal at a local device, wherein the second timing reference signal includes an internal timing reference, receiving a timing indication from a remote device, calculating a timing offset from at least one of a propagation delay, the timing indication, or the first timing reference signal, adjusting the internal timing reference based on the timing offset, and transmitting a message based on the internal timing reference.

System and method for processing an analog signal. For example, a demodulator for processing an analog signal includes one or more analog-to-digital converters configured to receive an analog signal and generate a digital signal based at least in part on the analog signal, and a correlator coupled to the one or more analog-to-digital converters and configured to generate a stream of correlation results including a first plurality of correlation results, a second plurality of correlation results, and a third plurality of correlation results. The first plurality of correlation results is different from the second plurality of correlation results by at least one correlation result, and the second plurality of correlation results is different from the third plurality of correlation results by at least another correlation result.