A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.

Doppler correlators are configured to receive samples of a signal sampled based on a frequency. Each Doppler correlator includes successive butterfly elements. Each butterfly element includes cross-coupled first and second branches that include a sample delay that doubles for each successive butterfly element, and a sample inversion selectively placed in one of the first and second branches to encode into the successive butterfly elements of each Doppler correlator the same code sequence. Each Doppler correlator is configured with a respective phase rotation that varies across the Doppler correlators. Each Doppler correlator is configured to correlate the samples against the code sequence and apply the respective phase rotation to the samples as the samples are shifted through the successive butterfly elements, to produce respective correlation results from each Doppler correlator centered on a respective frequency offset from the frequency that varies across the Doppler correlators based on the phase rotations.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

A Global Navigation Satellite System (GNSS) receiver demodulates code shift keying (CSK) data utilizing a binary search. The GNSS receiver receives a signal including a pseudorandom noise (PRN) code modulated by code shift keying (CSK) to represent a symbol (i.e., CSK modulated symbol). The GNSS receiver maintains a plurality of receiver codes each representing a different shift in chips to the PRN code. The GNSS receiver performs a linear combination of portions of the receiver codes. In an embodiment, the GNSS receiver compares correlation power level value for respective portions of the receiver codes to demodulate the CSK data. In a further embodiment, the GNSS receiver compares the correlation power level values for portions of receiver codes with power detection threshold values to demodulate the CSK data. In a further embodiment, the GNSS receiver utilizes signs of the correlation power level values to demodulate the CSK data.

Systems and methods are described for determining position of a receiver. The positioning system comprises a transmitter network including transmitters that broadcast positioning signals. The positioning system comprises a remote receiver that acquires and tracks the positioning signals and/or satellite signals. The satellite signals are signals of a satellite-based positioning system. A first mode of the remote receiver uses terminal-based positioning in which the remote receiver computes a position using the positioning signals and/or the satellite signals. The positioning system comprises a server coupled to the remote receiver. A second operating mode of the remote receiver comprises network-based positioning in which the server computes a position of the remote receiver from the positioning signals and/or satellite signals, where the remote receiver receives and transfers to the server the positioning signals and/or satellite signals.

A method of processing a satellite signal includes: receiving a satellite positioning system (SPS) signal, including an SPS data signal of unknown data content, from a satellite at a wireless communication device; receiving symbol indications, of determined symbol values, from a terrestrial wireless communication system at the wireless communication device; correlating the SPS data signal with a pseudo-random noise code to obtain first correlation results; and using the symbol indications and the first correlation results to determine a measurement of the SPS signal.

System and method for processing an analog signal. For example, a demodulator for processing an analog signal includes one or more analog-to-digital converters configured to receive an analog signal and generate a digital signal based at least in part on the analog signal, and a correlator coupled to the one or more analog-to-digital converters and configured to generate a stream of correlation results including a first plurality of correlation results, a second plurality of correlation results, and a third plurality of correlation results. The first plurality of correlation results is different from the second plurality of correlation results by at least one correlation result, and the second plurality of correlation results is different from the third plurality of correlation results by at least another correlation result.

Disclosed are a spread-spectrum decoding method for a transmitted signal and a display apparatus. The method comprises: acquiring a fixed input frequency of an input signal, and taking the fixed input frequency as a decoding frequency; performing a calculation according to the fixed input frequency to obtain a cycle number N of the input signal within a pre-set time range; determining whether, during the pre-set time range, the ratio of the number of cycles corresponding to the input frequency after the spread-spectrum processing, which is greater than or less than the decoding frequency, to the cycle number N is greater than or equal to a pre-set percentage; if so, adding a one stage pre-set adjustment frequency value to the decoding frequency or subtracting same from the decoding frequency so as to obtain a new decoding frequency; and taking the new decoding frequency as an updated decoding frequency.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

In some examples, a circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit and the output of the oscillator coupled to the second input of the PFD.