A demultiplexing device includes a first demultiplexer configured to demultiplex a first input signal, a second demultiplexer configured to demultiplex a second input signal, and a switching circuit configured to set an input destination of signals demultiplexed and output by each of the first demultiplexer and the second demultiplexer based on data rates of the first and second input signals. A multiplexing device includes a first multiplexer configured to multiplex a first input signal, a second multiplexer configured to multiplex a second input signal, and a switching circuit configured to set an input destination of signals multiplexed and output by the first multiplexer and the second multiplexer based on data rates of the first and second input signals.

A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal of the predetermined cycle length and the predetermined data rate; a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state; a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state; a first driver circuit configured to output a signal corresponding to a signal output from the first selector; and a second driver circuit configured to output a signal corresponding to a signal output from the second selector.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

Methods, systems, and devices for techniques for enabling and disabling of a serializer/deserializer are described. In some examples, a system may be configured to identify information to be transmitted by a serializer/deserializer over a communication channel and activate, based on identifying the information to be transmitted, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel. Additionally or alternatively, in some examples, a system may be configured to identify information to be received by a serializer/deserializer over a communication channel and activate, based on identifying the information to be received, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel.

A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

A serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer and a plurality of flip-flops coupled to the multiplexer. Each serializer unit cell contains a state machine defining operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

A serializer includes a recursive tree of serializer unit cells. Each serializer unit cell includes a multiplexer and a plurality of flip-flops coupled to the multiplexer. Each serializer unit cell contains a state machine defining operation of the corresponding serializer unit cell. The recursive tree is organized with upper level serializer unit cells disposed more closely to a serializer output than are lower level serializer unit cells. The recursive tree is configured such that each serializer unit cell that is adjacent to and in an upper position relative to a corresponding lower level serializer unit cell directs the corresponding lower level serializer unit cell to output data, and the corresponding lower level serializer unit cell communicates to the corresponding serializer unit cell when the corresponding lower level serializer unit cell is done outputting data.

A method is provided. The method, comprises: power amplifying, with at least two parallel power amplifiers, at least two pre-distorted signals each corresponding to a unique transmit band, wherein each power amplifier operates in a unique transmit band; and pre-distorting, with a single pre-distortion system, at least two signals in different transmit bands, where the pre-distortion of each of the at least two signals is based upon a portion of a corresponding power amplified, pre-distorted signal, and where the pre-distortion diminishes certain IMD products in the corresponding power amplified, pre-distorted signal.

A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.