A circuit structure for efficiently demodulating an FSK signal in a wireless charging device, comprising a data sampling module, a period point counting module, a data distribution module, and a period point processing module. An input terminal of the period point counting module is connected to an output terminal of the data sampling module; an input terminal of the data distribution module is connected to an output terminal of the period point counting module; and an input terminal of the period point processing module is connected to an output terminal of the data distribution module.

A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis.

Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

According to an embodiment, a signal conversion apparatus includes a control information generator and a selector. The control information generator generates first control information based on rate information indicating transmission rates of original signals. The first control information designates a first timing at which each of the original signals is sampled. The selector selects each of the sampled signals at a timing based on the first timing. The original signal group includes a first original signal at a first transmission rate and a second original signal at a second transmission rate. The first transmission rate is higher than the second transmission rate. The frequency of allocating the first timing to the first original signal is higher than a frequency of allocating the first timing to the second original signal.

TDM circuitry that includes a rotary multiplexer and a memory circuit is provided. A first rotary multiplexer circuit may receive N-bit wide data in accordance to a time division multiple access (TDMA) scheme. The N-bit wide data includes multiple sets of M-bit wide data. The first rotary multiplexer may rotate these sets of the M-bit wide data. The memory circuit is coupled to the first rotary multiplexer circuit. The memory circuit stores each of rotated set of M-bit wide data. A second rotary multiplexer circuit may read k-th bits of the each of the stored M-bit wide data from the memory circuit and may rotate these k-th bits before outputting these k-th bits serially, where k is an integer having a value greater than 0.

The present disclosure relates to phase alignment, in particular to phase alignment circuitry (and parts thereof) for example for use in a multiplexer or other circuitry in which data is transmitted from one stage to another. Consideration is given to phase detection and phase rotation. Such circuitry may be implemented as integrated circuitry, for example on an IC chip.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.

A method is provided. The method, comprises: power amplifying, with at least two parallel power amplifiers, at least two pre-distorted signals each corresponding to a unique transmit band, wherein each power amplifier operates in a unique transmit band; and pre-distorting, with a single pre-distortion system, at least two signals in different transmit bands, where the pre-distortion of each of the at least two signals is based upon a portion of a corresponding power amplified, pre-distorted signal, and where the pre-distortion diminishes certain IMD products in the corresponding power amplified, pre-distorted signal.