A display device is disclosed to include a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels coupled to the data lines and gate lines. The data lines include first and second data lines, and the pixels include first and second color pixels. The display device also includes a data driving circuit to generate data voltages through a plurality of output channels, a gate driving circuit coupled to the gate lines, and a timing controller to generate control signals to the data driving circuit and the gate driving circuit. The display device further includes a demultiplexer switching circuit with first demux switches to supply, when turned on, the data voltages from the output channels to the first data lines, and second demux switches to supply, when turned on, the data voltages from the output channels to the second data lines.

Provided is a method for controlling a time division duplexing (TDD) Tx/Rx switching timing in a cloud radio access network (CRAN) that can finely control a switching timing between transmission and reception of TDD signals with an additional component added to a digital unit (DU) and a radio unit (RU) in the CRAN.

Methods, systems, and devices for techniques for enabling and disabling of a serializer/deserializer are described. In some examples, a system may be configured to identify information to be transmitted by a serializer/deserializer over a communication channel and activate, based on identifying the information to be transmitted, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel. Additionally or alternatively, in some examples, a system may be configured to identify information to be received by a serializer/deserializer over a communication channel and activate, based on identifying the information to be received, both a transmission component and a reception component of the serializer/deserializer that are coupled with the communication channel.

A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.

The invention provides a method and apparatus that addresses and resolves the issues currently affecting the ability to offer Enhanced TV, in particular, those issues concerning timing and synchronization, interaction with other modules in the STB, and distribution.

A multilevel modulation optical transceiver for distributing an OTN frame defined by ITU-T to a plurality of lanes for transmission, the multilevel modulation optical transceiver including: an MLD transmission unit; and a data replication unit, further including a data rearrangement unit arranged at a preceding stage of the MLD transmission unit, for performing data rearrangement processing of replicating, in advance, a frame synchronization pattern of an overhead of the OTN frame before being subjected to the lane rotation processing from a first lane that has the overhead to another lane that does not have the overhead, and of saving a payload to be overwritten with the frame synchronization pattern to a reserved area of the overhead to enable the payload to be restored on a reception side.

A phase synchronized optical master-slave loop comprises at the slave-end a processor (105) configured to include a first timing signal into a bit stream to be transmitted to the master-end, detect a second timing signal from a bit stream received from the master-end, and calculate a phase difference between a regenerated phase signal and a reference phase signal on the basis of a transmission moment of the first timing signal, a first time-stamp indicating a reception moment of the first timing signal at the master-end, a reception moment of the second timing signal, and a second time-stamp indicating a transmission moment of the second timing signal from the master-end. The processor is configured to read the time stamps from the received bit stream that corresponds to a received light signal according to a reception line-code. Thus, conversion of data format is not necessary for the phase synchronization.

Integrated performance monitoring (PM); optical layer operations, administration, maintenance, and provisioning (OAM & P); alarming; amplification, and the like is described in optical transceivers, such as multi-source agreement (MSA)-defined modules. A pluggable optical transceiver defined by an MSA agreement can include advanced integrated functions for carrier-grade operation which preserves the existing MSA specifications allowing the pluggable optical transceiver to operate with any compliant MSA host device with advanced features and functionality, such as Forward Error Correction (FEC), framing, and OAM&P directly on the pluggable optical transceiver. The advanced integrated can be implemented by the pluggable optical transceiver separate and independent from the host device.

An output signal generation device includes: two or more signal output blocks that each include two or more serial output circuits and a signal multiplex unit, the serial output circuits controlling amplitudes of data signals having different delay times and each outputting a first serial signal, the signal multiplex unit electrically multiplexing the first serial signals outputted from the two or more serial output circuits, and output a second serial signal obtained by electrical multiplex of the signal multiplex unit; and a phase correction unit that controls a phase of the second serial signal outputted from the two or more signal output blocks by changing the amplitude of the first serial signal outputted from the serial output circuit.

An example calibration circuit for a receiver includes a first circuit coupled to decision circuits in the receiver. The decision circuits are configured to compare a signal to reference voltages at times based on clocks. The clocks have different phases. The first circuit is configured to receive an output of the decision circuits, generate, in response to the output, the reference voltages, the reference voltages being shifted from centers of data eyes at the decision circuits, and generate a control signal based on comparisons of the reference voltages. The calibration circuit includes a second circuit, coupled to the first circuit and the decision circuits, configured to output the clocks to the decision circuits and apply at least one correction in duty cycle to at least one of the clocks in response to the control signal received from the first circuit.