H04L1/0052

Decoding circuit

There is provided a decoding circuit including; a first decoding unit that decodes a first signal from a multiplexed signal in which the first signal and a second signal are multiplexed in an LDM (Layered Division Multiplexing) system; and a second decoding unit that decodes the second signal from the multiplexed signal using the decoding result of the decoded first signal, wherein the second signal is selectively decoded based on noise information related to a reception state of the multiplexed signal.

Dynamic frozen bits and error detection for polar codes

Methods, systems, and devices for wireless communication are described for dynamic frozen bits of polar codes for early termination and performance improvement. A wireless device may receive a signal comprising a codeword encoded using a polar code. The wireless device may perform decoding of the codeword including at least: parity check of a first subset of decoding paths for making a decision on early termination of decoding of the codeword based on dynamic frozen bits, and generating path metrics for a second subset of the decoding paths that each pass the parity check based on the dynamic frozen bits, and performing error detection on a bit sequence corresponding to one of the second subset of the decoding paths based at part on error detection bits and the generated path metrics. The wireless device may process the information bits based on a result of the decoding.

REDUCED COMPLEXITY CHANNEL CODING FOR REDUCED CAPABILITY NEW RADIO USER EQUIPMENT

Among other things, embodiments of the present disclosure are directed toward reducing the complexity associated with low density parity check (LDPC)-based channel coding employed for physical downlink and uplink shared channels (PDSCH and PUSCH) for reduced capacity (RedCap) new radio (NR) user equipments (UEs). Other embodiments may be disclosed and/or claimed.

LOW DENSITY PARITY CHECK DECODER AND STORAGE DEVICE

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

MIXING COEFFICIENT DATA FOR PROCESSING MODE SELECTION
20230113600 · 2023-04-13 · ·

Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data delayed versions of at least a portion of the respective processing results with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data delayed versions of respective outputs of various layers of multiplication/accumulation processing units (MAC units) for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a wireless processing mode selection. In another example, such mixing input data with delayed versions of processing results may be to receive and process noisy wireless input data. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.

Hybrid automatic repeat request (HARQ) technique based on receiver processing capability

This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer-readable media, for implementing a retransmission protocol in a wireless local area network (WLAN). The retransmission protocol may be based on a hybrid automatic repeat request (HARQ) protocol that supports a delayed acknowledgement for a HARQ retransmission based on receiver processing capability. A first WLAN device may determine that a second WLAN device requires more time to process the HARQ retransmission and may transmit a different communication (interlaced within the HARQ process) to either the second WLAN device or a third WLAN device during the time that the second WLAN device is processing the HARQ retransmission.

Byte-based error correction to improve for wireless networks

Improved error correction systems and methods for wireless networks are described herein. A method can include generating a first cyclic redundancy code (CRC) for a payload of a data packet by executing cycles for sets of input bytes from the payload using a CRC algorithm so as to reduce a number of the cycles required to generate the first CRC when compared to generating the first CRC from individual bits of the payload, appending the first CRC to the payload of the data packet, and transmitting the data packet over a wireless link from a source to a sink.

VERIFYING DATA INTEGRITY IN A RECEIVER
20230104186 · 2023-04-06 ·

A method for verifying data integrity in a receiver in a wireless communication network is disclosed. The method includes receiving a data message, wherein the data message includes a group of data elements and a checksum, computing a complete syndrome vector based on partial syndrome vectors, wherein the partial syndrome vectors are computed, in parallel, by multiplying part of a parity-check matrix with corresponding part of the received data message, determining that all vector elements of the complete syndrome vector are zero, and verifying that the received data message is correct when all the vector elements of the complete syndrome vector are zero, and incorrect otherwise. Corresponding computer program product, apparatus, and receiver are also disclosed.

METHOD AND APPARATUS FOR TRANSMITTING POSITIONING REFERENCE SIGNAL IN WIRELESS ACCESS SYSTEM SUPPORTING MACHINE TYPE COMMUNICATION
20170374640 · 2017-12-28 · ·

The present invention provides methods for configuring and transmitting a positioning reference signal (PRS) used for estimating the location of a machine type communication (MTC) terminal in a wireless access system supporting machine type communication (MTC), and an apparatus for supporting the same. According to one embodiment of the present invention, a method for transmitting, by a base station, a positioning reference signal (PRS) used for estimating the location of a machine type communication (MTC) terminal in a wireless access system supporting MTC, comprises the steps of: repeating transmission of a physical downlink shared channel (PDSCH) including the same downlink data N times; and transmitting the PRS in a PRS subframe (SF), wherein when the PRS SF consists of a normal subframe (SF) and a multimedia broadcast multicast service single frequency network (MBSFN) SF, a normal cyclic prefix (CP) is used as a CP to be applied to the PRS, and when the PRS SF consists of only the MBSFN SF, a CP applied to the PRS may be an extended CP.

Encoding and Decoding Method and Apparatus

Encoding methods and apparatuses are provided. The method includes: obtaining to-be-encoded information including K information bits and a mother code length N; determining, based on K and N, a set I corresponding to subchannels of the information bits, where information bits corresponding to subchannel sequence numbers in I are distributed in X outer-code subcodes including X1 first-type outer-code subcodes, quantities of information bits in the X1 first-type outer-code subcodes are P.sub.1, P.sub.2, . . . , and P.sub.X1, P.sub.i (i=1, 2, . . . , X1) is one of K.sub.1, K.sub.2, . . . , and K.sub.m, which are greater than a first threshold LB and less than a second threshold HB, 1=<m<(HB−LB−1), LB+1<HB, HB<=a length B of an outer-code subcode, X, HB, and B are positive integers, and LB is an integer >=0; and performing encoding based on I.