H04L1/0052

Method, apparatus and system for error control

A first device receives a first container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames, each of which includes an optical data unit (ODU) frame and a sequence of forward error correction (FEC) bits for the ODU frame. Each OTU frame is associated with a first sequence of error-identifying bits. The first device determines, for each OTU frame, a second sequence of error-identifying bits, and forms a second container frame including the OTU frames, the first sequences of error-identifying bits, and the second sequences of error-identifying bits. The first device transmits the second container frame to a second device.

VECTOR SIGNALING WITH REDUCED RECEIVER COMPLEXITY
20170294985 · 2017-10-12 ·

Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Code-block-based communication for random access channel

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a transport block that includes one or more code blocks carrying a random access channel (RACH) communication directed to the UE. The transport block may be segmented into the one or more code blocks based at least in part on a segmentation procedure specific to a RACH procedure. The user equipment may decode the one or more code blocks based at least in part on a code block cyclic redundancy check (CRC) associated with the one or more code blocks. Numerous other aspects are provided.

Decoder architecture for cyclically-coupled quasi-cyclic low-density parity-check codes

This invention provides a cyclically-coupled (CC-) quasi-cyclic (QC-) low-density parity-check (LDPC) code and its decoder architecture. The essence of the invention is to introduce the convolutional nature to a plurality of individual block codes internally so as to form a resultant block code with a prolonged code length while slightly increasing the hardware complexity in decoder realization. The CC-QC-LDPC code is formed by cyclically coupling a plurality of sub-codes each being a QC-LDPC code such that overlapping of some variable nodes between two consecutive sub-codes results. The decoder comprises plural sub-decoders each configured to decode the channel messages for one sub-code. The sub-decoders are arranged in a ring shape such that an individual sub-decoder is configured to communicate edge messages with two neighboring sub-decoders adjacent to said individual sub-decoder in the decoding of the channel messages. The sub-decoders are configured to operate concurrently for simultaneously decoding individual sub-codes.

Signal Processing Apparatus and Method
20170331588 · 2017-11-16 ·

A method of operating a signal processing apparatus (110) comprises receiving a first signal representing a received data bit, determining from the first signal a first soft data bit, storing the first soft data bit in a leaky storage device (130), receiving a second signal representing the received data bit, and determining from the second signal a second soft data bit. The stored first soft data bit is read from the leaky storage device (130), an elapsed leakage time of the stored first soft data bit is measured, and a third soft data bit is generated dependent on the stored first soft data bit read from the leaky storage device (130) and on the elapsed leakage time. A fourth soft data bit is generated by combining the second soft data bit and the third soft data bit, and the received data bit is decoded dependent on the fourth soft data bit and on a selected plurality of further received data bits.

APPARATUS FOR GENERATING BROADCAST SIGNAL FRAME FOR SIGNALING TIME INTERLEAVING MODE AND METHOD USING THE SAME

An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to perform power-normalizing for reducing the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time interleaving after performing the power-normalizing; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).

ENCODING METHOD AND COMMUNICATIONS DEVICE

Embodiments disclose an encoding method and a communications device. The method includes: obtaining and encoding a to-be-encoded information bit sequence based on a binary vector P.sub.1 of a first code, to obtain and output an encoded bit sequence, where P.sub.1 is determined based on a binary vector P.sub.2 of a second code and a binary vector P.sub.3 of a third code, P.sub.1, P.sub.2, and P.sub.3 indicate an information bit and a frozen bit of the first code, the second code and the third code respectively, a code length of the first code, the second code and the third code is n.sub.3, n.sub.2 and n.sub.3 respectively, a quantity of information bits of the first code, the second code and the third code is k.sub.1, k.sub.2 and k.sub.3 respectively, n.sub.1=n.sub.2*n.sub.3, and k.sub.1=k.sub.2*k.sub.3. Therefore, parallel decoding can be performed, helping reduce a decoding delay.

Method and device in UE and base station for channel coding

The disclosure discloses a method and device in UE and a base station for channel coding. A first node first determines a first bit block and then transmits a first radio signal, wherein bits of the first bit block are used to generate bits of a second bit block, a third bit block comprises bits of the second bit block and the first bit block, and the third bit block is used to generate the first radio signal. The first bit block, the second bit block and the third bit block comprise P1, P2 and P3 bits, respectively.

FULLY PARALLEL TURBO DECODING
20170244427 · 2017-08-24 ·

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

MULTI-MODE UNROLLED POLAR DECODERS
20170230059 · 2017-08-10 ·

There is described a multi-mode unrolled decoder. The decoder comprises a master code input configured to receive a polar encoded master code of length N carrying k information bits and N−k frozen bits, decoding resources comprising processing elements and memory elements connected in an unrolled architecture and defining an operation path between the master code input and an output, for decoding a polar encoded code word, at least one constituent code input configured to receive a polar encoded constituent code of length N/p carrying j information bits and N/p−j frozen bits, where p is a power of 2, and at least one input multiplexer provided in the operation path to selectively transmit N/p bits of one of the master code and the constituent code to a subset of the decoding resources.