Patent classifications
H04L1/0054
Data checking method and device
Provided are a data checking method and device. The method includes: receiving a transmission signal containing a first data block and transmitted by a transmission node, wherein the length of the first data block is N bits, the first data block is generated by performing an FEC encoding on a second data block which has a length of K bits, and the second data block is generated by performing a CRC encoding on a third data block which has a length of L bits, where N, K and L are all positive integers, and N≧K>L; obtaining a first estimation data block of the first data block according to the transmission signal, and obtaining a second estimation data block of the second data block according to the transmission signal; and checking the third data block according to a relationship between the first estimation data block and an FEC code space and/or a CRC check result of the second estimation data block. By means of the technical solution provided in the present disclosure, the problems that a transmission rate decreases due to the fact that a CRC check code is too long and a false detection rate cannot be ensured due to the fact that the CRC check code is too short are solved.
IMPROVED SIGNALING TECHNIQUES IN THE PRESENCE OF PHASE NOISE AND FREQUENCY OFFSET
Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.
Reference Time Generator
A reference time generator including a first clock source including a reference synthesizer and cesium atomic clock configured to produce a cesium reference signal and a cesium QOT metric, a second clock source including a reference synthesizer and rubidium atomic clock configured to produce a rubidium reference signal and a rubidium QOT metric, and a circuit for selecting from the clock sources one reference signal based on the best QOT metric.
ENHANCED LVA DECODING USING ITERATIVE COMPARISON TRELLIS CONSTRUCTION
The described techniques relate to improved methods, systems, devices, or apparatuses that support enhanced efficiency in list Viterbi algorithm (LVA) decoding using iterative comparison trellis construction. Iterative comparison may involve comparison and selection from ordered accumulated path metrics associated with feeding transitions by selecting, for each successive rank of an ordered path metrics list for the current stage, the best unselected accumulated path metric of the feeding transitions. The iterative comparison may be performed sequentially for each stage before processing the next stage. Alternatively, the iterative comparison may be pipelined across stages, and different ranks of the ordered path metrics lists for different stages may be concurrently computed in a single trellis search cycle using multiple comparators. Iterative comparison may be used in an inner decoder to generate an ordered path metrics list for processing according to an error checking function using an outer decoder.
RECEPTION DEVICE, RECEPTION METHOD, AND TRANSMISSION RECEPTION SYSTEM
Provided are a reception device, a reception method and a transmission reception system capable of reducing the influence of distortion in a received signal and achieving high demodulation performance without performing a computation process having a great amount of calculations. The reception device receives a signal containing a known signal part and a data part, and includes a conversion unit that converts the signal received by a reception unit into a digital signal, a region determination unit that determines a nonuse region which is a periodic region containing distortion in the digital signal, on a basis of a first digital signal in the known signal part contained in the digital signal and a known signal held in advance, and a demodulation unit that performs demodulation on the digital signal by using a second digital signal in a region other than the nonuse region in the digital signal.
Low power downlink control channel monitoring
Methods, systems, and devices for wireless communications are described. In some systems, a user equipment (UE) may monitor sets of decoding candidates over a search space in each monitoring occasion to detect downlink control transmissions. Such a monitoring process may be resource intensive. To reduce the processing power involved in monitoring the control channel, a UE may measure resources associated with the downlink control channel to obtain a quality metric. The UE may compare the quality metric to one or more thresholds and may perform a decoding process on a set of configured decoding candidates for the downlink control channel based on the comparing. In some cases, if the channel quality is relatively good, the UE may perform a list decoding process using a list size less than a maximum list size or may perform partial data tone processing to reduce the processing complexity for some of the decoding candidates.
Reception device and reception method
A reception device includes: a receiver that receives a multiplexed signal; a first demapper that demaps the multiplexed signal, with a second modulated symbol stream of a second data series being included in the multiplexed signal as an undefined signal component, to generate a first bit likelihood stream of a first data series; a second demapper that demaps the multiplexed signal, with a first modulated symbol stream of the first data series being included in the multiplexed signal as an undefined signal component, to generate a second bit likelihood stream of the second data series; a first decoder that performs error control decoding on the first bit likelihood stream to derive the first data series; and a second decoder that performs error control decoding on the second bit likelihood stream to derive the second data series.
ENHANCED POLAR CODE CONSTRUCTIONS BY STRATEGIC PLACEMENT OF CRC BITS
Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
GENERALIZED POLAR CODE CONSTRUCTION
Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits using a first code of length K to obtain bits for transmission via K channels, wherein the first code comprises a polar code, further encoding the bits in each of the K channels using a second code of length M, and transmitting the codeword.
ENCODING AND DECODING OF CONTROL SIGNALING WITH SECTIONAL REDUNDANCY CHECK
Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes obtaining a payload to be transmitted, partitioning the payload into a plurality of payload sections, deriving redundancy check information for each respective payload section of the plurality of payload sections, merging the redundancy check information for each payload section with the plurality of payload sections to form a sequence of bits, and generating a codeword by encoding the sequence of bits using an encoder. Other aspects, embodiments, and features are also claimed and described.