The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit. The ML detecting circuit executes the following steps: selecting K first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof; calculating K second-layer candidate values according to the K first-layer candidate values; determining whether to add P second-layer supplemental candidate value(s) and generating a decision; when the decision is affirmative, adding the P second-layer supplemental candidate values, generating P first-layer supplemental candidate values according to the P second-layer supplemental candidate values, and calculating log likelihood ratios (LLRs) according to the (K+P) first-layer and (K+P) second-layer candidate values; and when the decision is negative, calculating LLRs according to the K first-layer and K second-layer candidate values.

The present disclosure includes an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a search value according to a communication index and a modulation type or determine the search value according to a predetermined value, in which the communication index is related to a reception signal or a derivative thereof, the search value is associated with a search range, and a number of candidate signal value(s) in the search range is not greater than a number of all candidate signal values of the modulation type. The ML detecting circuit is configured to execute an ML calculation according to the search value and one of the reception signal and the derivative thereof, so as to calculate a log likelihood ratio of every candidate signal value in the search range.

Embodiments of a device and method are disclosed. In an embodiment, a method of wireless communications involves at a receiver, receiving a first packet, subsequently, at the receiver, receiving a second packet, and determining whether the second packet is a repetition of the first packet based on packet acquisition information associated with the first and second packets.

A transmitter may comprise a symbol mapper circuit and operate in at least two modes. In a first mode, the number of symbols output by the mapper circuit per orthogonal frequency division multiplexing (OFDM) symbol transmitted by said transmitter may be greater than the number of data-carrying subcarriers used to transmit the OFDM symbol. In a second mode, the number of symbols output by said mapper circuit per orthogonal frequency division multiplexing (OFDM) symbol transmitted by said transmitter is less than or equal to the number of data-carrying subcarriers used to transmit said OFDM symbol. The symbols output by the symbol mapper circuit may be N-QAM symbols. While the circuitry operates in the first mode, the symbols output by the mapper may be converted to physical subcarrier values via filtering and decimation prior to being input to an IFFT circuit.

The present technology provides a system and methods for carrier frequency offset (CFO) estimation. According to embodiments, there is provided a system and method for CFO estimation for narrow band 3GPP LTE/LTE-A Machine Type Communication (MTC) uplinks.

A decoding apparatus includes a plurality-of-bits decoding part configured to receive an input vector obtained by adding a message encrypted by a trapdoor function and an error vector including an element(s) conforming with a discrete Gaussian distribution, and decode a plurality of bits from a lower bit of the message based on the input vector in correctness with a predetermined probability; and a confirmation calculation part configured to determine in parallel whether the decoded plurality of bits are correct or not, wherein the message is encrypted by taking an inner product with a vector including a power of two as an element(s).

Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Embodiments of the invention provide a decoder for decoding a signal received through a transmission channel in a communication system, said signal comprising a vector of information symbols, said transmission channel being represented by a channel matrix, wherein the decoder comprises: an initial radius determination unit (307) configured to determine an initial radius; a symbol estimation unit (309) configured to iteratively determine a current radius to search a lattice point inside a current spherical region defined by said current radius, said current radius being initially set to said initial radius, said symbol estimation unit (309) being configured, for each lattice point found in said current spherical region, to store said lattice point in association with a metric, said symbol estimation unit (309) being further configured to update said current radius using a linear function, said linear function having a slope parameter strictly inferior to one,

The decoder being configured to determine at least one estimate of said vector of information symbols from at least one of the lattice points found by the symbol estimation unit (309).

A technique for assessing the reliability of bits received by a modulation symbol on a channel is provided. A providing circuit provides an input dataset including a plurality of input values. The input values correspond to different transmit hypotheses according to a modulation alphabet used for encoding the bits in the symbol. A computing circuit performs a first computing step and a second computing step. In the first computing step, a first intermediary dataset is computed by combining the input values of the input dataset according to a first combination scheme. In the second computing step, a second intermediary dataset is computed by combining the input values of the input dataset according to a second combination scheme. The second combination scheme is different from the first combination scheme. An assessing circuit assesses the reliability of the bits based on the first intermediary dataset and the second intermediary dataset.

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present disclosure provides a method for transmitting messages using a channel combining/splitting transmission scheme. The method comprises the steps of: splitting the messages into a first part to be transmitted to a first channel, which is a degradation channel, and a second part to be transmitted to a second channel, which is an enhancement channel, generating first modulation signals by performing a channel encoding and frequency quadrature amplitude modulation (FQAM) on the first part and generating second modulation signals by performing a channel encoding and quadrature amplitude modulation (QAM) on the second part, generating first transmission signals by combining the first modulation signals with a part of or all the second modulation signals and generating second transmission signals using the second modulation signals, and transmitting the generated first transmission signals and second transmission signals through the first channel and the second channel, respectively.