Patent classifications
H04L1/0082
Systems and methods for fast control messaging for multiple numerology access zones
A method is provided for detecting an access zone configuration of a downlink wireless transmission received from a wireless network by a receiver. The method includes steps of activating the receiver, synchronizing the receiver with the wireless network, detecting, by the receiver after the step of synchronizing, a received access zone of the downlink wireless transmission, determining a base symbol of the detected access zone, ascertaining a first gap and a second gap from repetitive information contained within the determined base symbol, concluding, from the ascertained first and second gaps, that the detected access zone is part of a multiple access zone configuration, and registering, after the step of concluding, the receiver with the wireless network.
Error handling in transactional buffered memory
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
Methods, a wireless device, a radio network node for managing a control block
Methods, a wireless device (110) and a radio network node (120) for managing a control block are disclosed. An extended Temporary Flow Identifier, eTFI, is assigned to the wireless device (110) by the radio network node (120). The radio network node (120) constructs the control information. The radio network node (120) performs a bit-wise modulo two addition with a control block and a combination of the eTFI and a pre-determined bit pattern to obtain a modified control block. The radio network node (120) adds channel coding redundancy. The radio network node (120) maps the modified control block onto physical resources. The radio network node (120) sends the modified control block to the wireless device (110). The wireless device (110) decodes the received modified control block removing the channel coding redundancy, performs a bit-wise modulo two addition between the modified control block and a combination of the eTFI and a pre-determined bit pattern to obtain a control block. The wireless device (110) decodes the control block using FIRE-decoding to obtain the control information. The wireless device (110) determines it is the intended recipient of the control information if the TFI information therein matches its assigned TFI. Corresponding computer programs and carriers therefor are also disclosed.
Referenceless clock and data recovery circuits
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.
MEMORY ARCHITECTURE INCLUDING RESPONSE MANAGER FOR ERROR CORRECTION CIRCUIT
A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
REFERENCELESS CLOCK AND DATA RECOVERY CIRCUITS
Referenceless clock and data recovery circuits are described that operate to align the clock/data strobe with each data eye to achieve a low bit error rate. The appropriate frequency and phase to be used is determined by an edge counter based frequency error detector and a phase error detector.
Method of communication between nodes in a network
A method of communicating between nodes in a network where a node receives a sequence of symbols that will form a packet on a first communications channel and has a planned packet that it would send on a second communications channel. A destination is encoded into an arbitration portion of a header sequence of the packet, the header sequence comprising a sequence of symbols. The transmission on the second communications channel is as per the planned packet, for as long as the symbols of the planned packet match the symbols being received on the first channel. An arbitration decision is made when the symbols do not match, with the node either continuing to send the rest of the planned packet, or the rest of the packet being received on the first communications channel.
Introduction and detection of erroneous stop condition in a single UART
A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.
Method and apparatus for removing jitter in audio data transmission
In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for removing jitter introduced by a packet switched network. Each received audio frame comprises a primary portion and a redundancy portion. The redundancy portion comprises a partial redundant copy of a previous frame that is offset by k frames. If a frame n is lost, a frame n+k that comprises the partial redundant copy of the lost frame n, is located in a jitter buffer. Based on the frame n+k, a substitute frame n substituting the lost frame n is created and a substitution indicator of the substitute frame n is set to indicate that the redundancy portion of the substitute fame n should be used in decoding.
METHOD AND APPARATUS FOR REMOVING JITTER IN AUDIO DATA TRANSMISSION
In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for removing jitter introduced by a packet switched network. Each received audio frame comprises a primary portion and a redundancy portion. The redundancy portion comprises a partial redundant copy of a previous frame that is offset by k frames. If a frame n is lost, a frame n+k that comprises the partial redundant copy of the lost frame n, is located in a jitter buffer. Based on the frame n+k, a substitute frame n substituting the lost frame n is created and a substitution indicator of the substitute frame n is set to indicate that the redundancy portion of the substitute fame n should be used in decoding.