A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.

Some implementations of the disclosure are directed to symbol-timing tracking systems and methods. A symbol-timing tracking system may include: an ADC to generate a digital signal by sampling an analog signal received at a receiver; an interpolator to adjust a sampling rate of the digital signal; a receive filter to apply a receive filtering function to the digital signal to generate a filtered signal; a timing error detector configured to generate a timing error signal from the filtered signal; a high-order loop filter to filter the timing error signal to generate a filtered timing error signal; and a numerically controlled oscillator to control timing data based on the filtered timing error signal and provide the timing data to the interpolator, wherein the interpolator is to correct for timing of the digital signal and adjust the sampling rate of the digital signal based on the timing data.

A 100BASE-TX transceiver includes a receive (RX) circuit, a transmit (TX) circuit, and a noise reduction circuit. The RX circuit receives an input data according to an RX clock, to generate an RX data. The TX circuit transmits a TX data according to a TX clock, to generate an output data, wherein the TX clock is constrained to be in sync with the RX clock. The noise reduction circuit applies noise reduction to the RX data according to the TX data, to generate a noise-reduced RX data.

A transmission device of the disclosure includes: a clock signal transmitting circuit that outputs a clock signal onto a clock signal line; a data signal transmitting circuit that outputs a data signal onto a data signal line; and a blanking controller that controls the clock signal transmitting circuit to output a predetermined blanking signal, in place of the clock signal, from the clock signal transmitting circuit to the clock signal line in synchronization with a blanking period of the data signal.

A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, a signal output and a rate control input. The VRCF is configured to receive a rate control signal at the rate control inputs and sample an input signal received at the signal input at a sampling rate controlled by a rate control signal to produce a VRCF output signal. The sampling rate is one of greater than and less than a sampling rate of the input signal. The VRCF has a first delay. The interface includes a first in first out, FIFO, buffer having an input and an output, the FIFO buffer configured to store samples of the VRCF output signal received at the FIFO buffer.

Receivers, controller units for receivers and related methods are provided. One receiver includes an adjustable sample provider providing samples of an input signal using an adjustable sample timing and a feedback path providing a feedback signal to the adjustable sample provider based on a timing error. The feedback path includes a loop filter providing sample timing information to the adjustable sample provider and a replacement value provider providing a replacement sample timing information replacing the sample timing information when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation. The replacement value provider provides the replacement sample timing information considering a timing error information over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.