The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

An object of the present invention is to provide a communication system and a communication method that can avoid network congestion using a simple approach. The communication system of the present invention is characterized in that a time distribution server that transmits time information to terminals distributes a time different from the standard time for each terminal, and the terminal performs communication on the basis of the distributed time, and further characterized in that, for a time synchronizing packet transmitted from a time distribution server on the Internet to a terminal, a node or the like in the middle of the path performs transfer control or rewrites the packet, thereby causing the terminal to recognize a different time, and the terminal performs communication on the basis of the time.

A method and system for synchronizing computers includes a bit computing module for computing of a bit by each computer, an exchange module, a bit signal pair determination module for determining a bit signal pair including the computed bit, a bit product pair determination module for determining a bit product pair indicating which bit equal to 1 of the bit signal pair of a computer can be combined with the bit of the bit signal pair determined for the other computer in the iteration n−1, a bit remainder pair determination module for determining a bit remainder pair indicating which bit equal to 1 of the bit signal pair of a computer in the iteration n is different from the bit of the bit signal pair of the other computer in the iteration n−1, a synchronized signal determination module for determining a synchronized signal based on the bit product pair and on the bit remainder pair.

A method for measuring asynchronous timestamp requests includes receiving a timestamp (“TS”) request from a client device during a first interval of a time of day (“TOD”) clock, and calculating, using the TOD clock, at a next interval of the TOD clock, a TS correction of the TS request relative to a reference point of the first TOD clock interval. The method further includes adding the TS correction to the reference point of the first interval of the TOD clock, and outputting the corrected TS to the client device.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.

A signal transceiver circuit, a method of operating a signal transmitting circuit, and a method of setting a delay circuit are provided. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter (DAC) for converting a first digital signal into the output signal according to the first clock; a second DAC for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter (ADC) for converting the analog signal into a second digital signal.

A line card receives a SYNC input signal and a first system clock signal. The line card generates a second system clock signal in a PLL and generates a SYNC output signal by dividing the second system clock signal in a divider circuit. The SYNC output signal is fed back as a SYNC feedback signal. The line card determines determining a closest edge of the first system clock signal to a transition of the SYNC input signal and determines a time difference between the closest edge of the first system clock signal and a transition of the SYNC feedback. The SYNC output signal is adjusted based on the time difference using a coarse adjustment by adjusting a divide ratio of the divider circuit and using a fine adjustment in the PLL based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.