An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

A line card of a network box receives a SYNC input signal and generates a first time stamp based on receipt of the SYNC input signal. The line card generates a system clock signal in a phase-locked loop and generates a SYNC output signal by dividing the system clock signal in a divider circuit. The SYNC output signal is fed back to an input terminal as a SYNC feedback signal. A time stamp is generated based on receipt of the SYNC feedback signal. The line card determines a time between the SYNC input signal and the SYNC feedback signal based on the first time stamp and the second time stamp. The timing of the SYNC output signal is adjusted based on the time difference using a coarse time adjustment by adjusting a divide ratio of the divider circuit and using a fine time adjustment in the phase-locked loop based on a residue of a remainder of the time difference not accounted for by the coarse time adjustment.

Systems and methods of this disclosure can operate to synchronize timing between communication devices and can include a timing server. The timing server can provide a communications interface for the exchange of timing messages to a first communication device. Using existing protocol messages defined in the M-CMTS architecture, additional communication devices can intercept, snoop, and extract timing information from messages between the first communication device and the timing server to adjust their internal clocks to maintain timing synchronization thereby reducing the number of communication interfaces required from a timing server.

A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.

A system and method for measuring propagation delays and other delays in an optical switching system. A transmitter is connected, through a circuit switch, to a receiver. To measure the propagation delay between the transmitter and the receiver, the transmitter sends one or more time-tagged ranging messages and the receiver calculates a propagation delay from the difference between the time of receipt and the time of transmission. In another embodiment, a time delay between message transmission and transition of a CDR of the receiver to a fast acquisition mode is adjusted, by trial and error, to find a range of such time delays for which transmission is successful. A time delay between the transmitter and the switch is measured by establishing or breaking the connection and determining, for various tentative time delay values, whether transmission succeeds.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

The Data Recovery with Inverse Transformation (DRIT) comprises methods and systems for reversing transmission channel transfer function in order to achieve a direct recovery of original data from a received signal distorted by a transmission link.

The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.