The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

An information processing apparatus that includes processing circuitry that: acquires information regarding a processing content to be performed by a terminal; acquires information regarding a designated time at which the terminal is designated to perform the processing content; acquires a selection of a base time zone from a plurality of time zones including at least a first time zone to which the information processing apparatus belongs and a second time zone to which the terminal belongs, the designated time being corrected according to the selected base time zone to set an execution time at which the terminal performs the processing content; and transmits an instruction to the terminal to perform the processing content at the execution time.

Techniques described herein may be used for determining an offset between clocks in a network. Such techniques may include obtaining, by a passive time device, a first timestamp pair corresponding to a first time protocol message; obtaining, by the passive time device, a second timestamp pair corresponding to a second time protocol message; and calculating, by the passive time device, a clock offset between a time protocol master and the passive time device using the first timestamp pair, the second timestamp pair, and a pre-determined time delay constant corresponding to a network tap.

To provide a transmission apparatus, a reception apparatus, and a transmission system that operate at the same clock as the reception apparatus without mounting an oscillation circuit on the transmission apparatus and realize a low error rate.

A transmission apparatus includes a first reception circuit, and a first transmission circuit, in which the first reception circuit receives a clock from the reception apparatus, and the first transmission circuit synchronizes retention data retained by the first transmission circuit using the received clock, and transmits the retention data to the reception apparatus.

A method of estimating a clock frequency offset in a mobile device relative to a clock frequency of a controller within a UWB network comprises (a) determining, for each of a plurality of anchors, an anchor clock frequency offset relative to the controller clock frequency, (b) broadcasting an anchor data packet from each anchor, the anchor data packet including the respective anchor clock frequency offset, (c) receiving at least one anchor data packet at the mobile device, (d) estimating a mobile device clock frequency offset relative to the anchor clock frequency of the anchor from which the at least one anchor data packet was received, and (e) estimating the clock frequency offset in the mobile device based on the estimated mobile device clock frequency offset and the anchor clock frequency offset included in the at least one received anchor data packet. Furthermore, a TDoA-based localization method and a TDoA-based localization system are described.

Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.

Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.

Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

A clock generating circuit includes a first frequency multiplier configured to generate a second clock signal having a second frequency based on a first clock signal having a first frequency, and a second frequency multiplier configured to generate a third clock signal having a third frequency based on the second clock signal. The first frequency multiplier includes a circuit configured to control a duty cycle of the first clock signal, a delay circuit configured to receive the duty controlled clock signal, and delay the received signal based on a duty cycle of the second clock signal to output a first delay clock signal, and an XOR gate configured to perform an XOR computation using the duty controlled clock signal and the first delay clock signal to output the second clock signal. The second frequency is greater than the first frequency, and the third frequency is greater than the second frequency.