The present invention relates to a network packet broker device including a deep packet matching module which controls a GTP correlation module to match a GTP control plane packet and a GTP user plane packet and a deep packet matching method thereof. Packet information in a deep stage at a switch level is extracted to match flows of the GTP control plane packet and the GTP user plane packet and a correlation may be assigned to forward the GTP control plane packet and the GTP user plane packet to the same egress port.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft, Overwatch, H1Z1, PUBG, Fortnite, Realm Royale, Planet Side 2, real-time strategy games, slot machines, electronic poker tournaments, etc.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

A device determines a first latency value of a first data flow from a first physical port of the device to a second physical port of the device and a second latency value of a second data flow from the second physical port to the first physical port, where the first latency value is less than the second latency value. The device determines a first target latency value based on the first latency value and the second latency value. The device adjusts a latency value of the first data flow to the first target latency value.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.

Devices and methods for calibrating communication lines are disclosed. A clock sets a frequency of transmission through a communication line. A delay compensator, comprising multi-tap delay lines introduces delays in a transmitted message to compensate for skew in the communication line. An error comparator, coupled to the delay compensator, identifies errors in the messages transmitted through the multi-tap delay lines above an error margin. A delay selector, coupled to the error comparator and to the delay compensator, selects taps of the multi-tap delay lines of the delay compensator. Taps of the multi-tap delay lines where no errors are identified for the selected clock frequency are stored in a memory.

A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.

Techniques for employing precise transmission capabilities of a physical (PHY) layer to transmit time-synchronization beacons at an edge-of-field-resolution increment of a field of MAC layer frame. In some examples, the PHY layer may transmit beacons with a greater precision than permitted by lower-resolution MAC layer header fields. The communication protocol may specify the size of the field that is populated with timing information at a first precision. However, the PHY layer may be capable of transmitting with a second precision that is greater than the first precision. Thus, to virtually increase the time-synchronization resolution of the beacons, the beacons may be transmitted by the PHY layer at an edge-of-field resolution of the MAC layer header field. In this way, the first precision of the timing information in the MAC layer header field is virtually increased to the second precision of the PHY layer.