The present invention relates to a network packet broker device including a deep packet matching module which controls a GTP correlation module to match a GTP control plane packet and a GTP user plane packet and a deep packet matching method thereof. Packet information in a deep stage at a switch level is extracted to match flows of the GTP control plane packet and the GTP user plane packet and a correlation may be assigned to forward the GTP control plane packet and the GTP user plane packet to the same egress port.

Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.

Disclosed is a method for determining respective transmission delays between a node and a plurality of radiators of an infrared audio transmission system comprising a signal generator and said plurality of radiators connected to said signal generator by a network, the method comprising, at a node of said network, transmitting at least one test signal to said plurality of radiators over said network, detecting an event triggered by said at least one test signal, and determining respective transmission delays between said node and said radiators on the basis of said event. Also disclosed are non-transitory computer program product comprising code means configured to cause a processor to carry out the method, a configuration node for carrying out the method, and a system comprising the configuration node and the plurality of radiators.

A signal conditioner for use in a serial data communications link. The signal conditioner including a tunable delay element responsive to a tuning signal to provide time domain delay modulation of the input data signals to generate conditioned (output) data signals, and phase comparator circuitry to generate the delay tuning signal based on a detected phase error between feedback conditioned data signals, and a reference signal. The tunable delay element and the phase comparator circuitry forming a delay-locked tuning loop to phase lock the conditioned data signals to the reference signal, independent of voltage domain frequency response. An example signal conditioner is a jitter attenuator/cleaner, where the bandwidth of the reference signal is lower than the bandwidth of the delay-locked tuning loop, to provide a low-jitter reference signal.

A master node of a distributed acquisition system is provided. The master node includes a communication interface for interfacing between a control component and a bus and the control component. The bus is coupled to one or more slave nodes distributed in the acquisition system. The control component is configured to acquire a configuration that provides a definition for a packet interval, wherein the packet interval definition provides an adequate timing margin to ensure that communication packets transmitted by the master node and the one or more slave nodes occur only at harmonics of the packet interval definition, distribute a time reference packet of the communication packets based on the packet interval definition via the bus to all of the slave nodes of the distributed acquisition system, and schedule transmission of communication packets transmitted by the master node via the bus to the one or more selected slave nodes based on the packet interval definition.

The present invention relates to an adaptive synchronization device for demodulating a signal in linear modulation (x). The device functions from a sampled version of the signal (x). The device being characterized in that it comprises: at least one synchronization module (F) comprising: at least one first sub-module (F.sub.n) arranged to deliver a first output signal (y) from the input signal (x) received at a period (T) less than the value (I) with (B) the bandwidth of the input signal (x); this first sub-module (F.sub.n) is capable of compensating a transmission delay of the input signal (x) by estimation of the propagation delay () between a transmitter and a receiver of a transmission medium; this first sub-module adapts the rate at its output to one sample per symbol; at least one second sub-module (F.sub.u) arranged to deliver a corrective () to be applied to the current estimation of the delay (), from an error term (w) defining the decision error of the device and the influence of the processings downstream of the first sub-module (F); at least one correction module of transmission imperfections (H), disposed downstream of the synchronization module (F) and forming a correction chain of transmission imperfections of the first output signal (y) received by this module (H) at the rhythm T, and comprising: at least one first sub-module (H.sub.n) arranged to deliver a second output signal (z) at the rhythm (T) estimating a stream of emitted symbols (ai); at least one second sub-module (H.sub.p) configured to deliver the error term (w), by application of a correction to an error term (v) for estimation of symbols to consider the influence of the processings included in the first sub-module (H.sub.n).

[00001]$\begin{array}{cc}\left(\frac{1}{B}\right)& \left(I\right)\end{array}$

An electronic device is provided. The electronic device includes a hardware timer, a memory, a communication circuit, and a processor. The processor is configured to measure a first time point of the hardware timer in response to a playback event received via the communication circuit from a master paired with the electronic device, calculate a second time point by adding a predefined first time interval to the first time point, and execute an instruction to play back a sound source at the second time point. A first resolution of the hardware timer is set to be higher than a second resolution of an operating system (OS).

This VR viewing system is configured such that an external computer 200 outputs sound from an external speaker 300 while an HMD 100 reproduces a VR moving image by means of a built-in computer. The external computer 200 performs a sound output to the external speaker 300, conducts a master management of a reproduction elapsed time of the VR moving image so as to be synchronized with the sound output, detects a difference between the reproduction elapsed time of the VR moving image by the built-in computer of the HMD 100 and the reproduction elapsed time of the VR moving image undergoing the master management by the external computer 200, and adjusts the reproduction of the VR moving image by the built-in computer so as to eliminate the detected difference.

A data transmission device includes an embedded clock-scheme differential signal transmission circuit and an in-phase signal transmission circuit. The data transmission device accepts transmission-object data and a transmission instruction for the data. Then, the data transmission device determines between the embedded clock-scheme differential signal transmission circuit and the in-phase signal transmission circuit, by which circuit to transmit the data, based on at least either one of the data and the transmission instruction. The data transmission device causes the determined circuit to transmit the data.

A CAN transceiver includes a first terminal which receives a transmit signal from a CAN microcontroller. A splitter unit transmits a signal derived from the transmit signal to a CAN bus a via bus connection. A unit receives signals from the CAN bus via the bus connection. A second terminal sends a receive signal derived from the received signals to the CAN microcontroller. The transmit and receive signals include a pulsed signal waveform which represents data bits. Delay circuits apply a deliberate delay to the rising or falling edge of pulses of the transmit signal and/or a deliberate delay to the rising or falling edge of pulses of the receive signal.