One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft?, Overwatch?, H1Z1?, PUBG?, Fortnite?, Realm Royale?, Planet Side 2?, real-time strategy games, slot machines, electronic poker tournaments, etc.

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

A transceiver and a clock generation module are provided. The transceiver includes a receiver and the clock generation module. The receiver receives a receiving-input-data and a receiving-input-strobe. The receiver includes a data-receiving circuit for delaying the receiving-input-data and a strobe-receiving circuit for delaying the receiving-input-strobe. The clock generation module includes a calibration circuit, a phase-compensation module, and a multi-phase signal generator. The phase-compensation module compensates one of the data-receiving circuit and the strobe-receiving circuit according to a data-phase-compensation signal and a strobe-phase-compensation signal generated by the calibration circuit. The multi-phase signal generator generates shifted system-clock signals. A phase difference between the first and the second shifted system-clock signals is equivalent to a phase difference between the receiving-path-data and the receiving-path-strobe.

The present invention discloses a method for configuring an operation mode of a remote transceiver unit connected to an access node via a communication line, the remote transceiver unit being operable in at least two operation modes: a Time Division Duplex, TDD, mode and a full duplex, FDX, mode; the method comprising, by the access node: a) obtaining a channel characteristic derived from channel measurements performed over the communication line, b) determining the operation mode of the remote transceiver unit as the FDX mode or the TDD mode based on the channel characteristic; c) transmitting an indication indicating the determined operation mode to the remote transceiver unit.

According to one embodiment, ao electronic device executes decision feedback-type equalization for input data using a tap coefficient while updating the tap coefficient. The electronic device includes a first memory cyclically receiving a tap coefficient, holing the tap coefficient received, and cyclically outputting the tap coefficient held, and a second memory receiving the tap coefficient cyclically output from the first memory and holding the tap coefficient received. The tap coefficient cyclically output from the first memory is delayed by at least one cycle than the tap coefficient cyclically received by the first memory. The tap coefficient held in the second memory is used for the decision feedback-type equalization in a no-signal period in which no input data exist.

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

Disclosed is a method for determining respective transmission delays between a node and a plurality of radiators of an infrared audio transmission system comprising a signal generator and said plurality of radiators connected to said signal generator by a network, the method comprising, at a node of said network, transmitting at least one test signal to said plurality of radiators over said network, detecting an event triggered by said at least one test signal, and determining respective transmission delays between said node and said radiators on the basis of said event. Also disclosed are non-transitory computer program product comprising code means configured to cause a processor to carry out the method, a configuration node for carrying out the method, and a system comprising the configuration node and the plurality of radiators.

Provided is a node unit which is branch-connected to another communication node via a transport medium, the node unit comprising: a delay measurement unit which transmits a test signal for measuring a delay to an adjacent node unit of the branch-connected upper stage via the transport medium and detects a loopback signal to which the test signal is looped back via the adjacent node unit of the upper stage, thereby measuring an upper stage transmission delay between the adjacent node unit of the upper stage and the node unit; a delay summation unit which, when an adjacent node unit of the branch-connected lower stage exists, receives a lower stage transmission delay transmitted from the adjacent node unit of the lower stage, and calculates a summed transmission delay by summing the upper stage transmission delay and the lower stage transmission delay; and a control unit which transmits the summed transmission delay to the adjacent node unit of the upper stage.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Methods, systems, and apparatus for EM communications. One of the apparatus includes a super-regenerative amplifier (SRA) configured to receive a binary phase shift keying (BPSK) modulated signal and to output an amplitude signal as a function of changes in phase in the BPSK modulated signal; a pseudo synchronous demodulator that rectifies the amplitude signal and generates an envelope of the rectified amplitude signal; and an analog to digital converter that converts the amplitude values of the envelope to digital binary values.