A synchronization circuit, a semiconductor storage device, and a synchronization method provided herein, which are capable of performing synchronization on a small circuit scale, includes: a first delay circuit delaying a input synchronization signal by a first predetermined time to generate a first delay synchronization signal; a second delay circuit delaying the first delay synchronization signal by a second predetermined time to generate a second delay synchronization signal; a first synchronization circuit outputting a first output data generated by synchronizing the input data with the input synchronization signal; a second synchronization circuit outputting a second output data generated by synchronizing the input data with the first delay synchronization signal; and a resynchronization circuit resynchronizing the input data with the second delay synchronization signal to update the first output data to the first synchronization circuit when the first output data is inconsistent with the second output data.

A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

The application discloses Systems and methods for a data synchronization. The system may include a receiving module, an instruction generating module and a sending module. The receiving module may be configured to receive the first instruction. The first instruction may be used to instruct the start of data acquisition of the system. In response to receiving the first instruction, the instruction generating module may be configured to generate a second instruction. The second instruction may be used to trigger at least two sensors to acquire data. The sending module may be configured to send second instruction to at least two sensors respectively based on the first delay. The first delay causes the time difference between at least two sensors starting to acquire data less than the first preset threshold.

Systems, apparatuses, and methods for utilizing training sequences on a replica lane are described. A transmitter is coupled to a receiver via a communication channel with a plurality of lanes. One of the lanes is a replica lane used for tracking the drift in the optimal sampling point due to temperature variations, power supply variations, or other factors. While data is sent on the data lanes, test patterns are sent on the replica lane to determine if the optimal sampling point for the replica lane has drifted since a previous test. If the optimal sampling point has drifted for the replica lane, adjustments are made to the sampling point of the replica lane and to the sampling points of the data lanes.

Provided is a node unit which is branch-connected to another communication node via a transport medium, the node unit comprising: a delay measurement unit which transmits a test signal for measuring a delay to an adjacent node unit of the branch-connected upper stage via the transport medium and detects a loopback signal to which the test signal is looped back via the adjacent node unit of the upper stage, thereby measuring an upper stage transmission delay between the adjacent node unit of the upper stage and the node unit; a delay summation unit which, when an adjacent node unit of the branch-connected lower stage exists, receives a lower stage transmission delay transmitted from the adjacent node unit of the lower stage, and calculates a summed transmission delay by summing the upper stage transmission delay and the lower stage transmission delay; and a control unit which transmits the summed transmission delay to the adjacent node unit of the upper stage.

In general, aspects of this disclosure are directed towards techniques for using a computing device to perform the functionality of a vehicle key, so that the computing device may be used to automatically unlock the doors of a vehicle and/or to activate a previously-deactivated keyless ignition system. The computing device may be associated with a vehicle, including sending an identifier associated with the computing device to the vehicle via short-range communication. The computing device may also send to the vehicle, via short-range communication, at least one unlock door signal including an access code verifiable by the vehicle, and wherein receipt of the at least one unlock door signal by the vehicle enables the vehicle to unlock one or more of its doors without further user intervention.

A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

Method for temporally synchronizing the output of signals and/or temporally synchronizing the processing of captured signals on a plurality of input and/or output channels of an electronic circuit, comprising the following steps: (a) combining a number of channels, in particular a proportion of all channels of the circuit, to form a logical group; (b) retrieving the channel latency of each channel belonging to the group from a data source; (c) determining the greatest channel latency from all retrieved channel latencies and at least temporarily storing the greatest channel latency as the group latency; (d) for each channel belonging to the group: determining the temporal difference between the group latency and the retrieved channel latency of the respective channel and storing the determined difference as a channel-associated latency offset in a memory, in particular a memory of the circuit; and (e) influencing the signal propagation via a respective channel on the basis of at least its respective stored latency offset.

A method for processing a digital audio broadcast signal in a radio receiver, includes: receiving a hybrid broadcast signal; demodulating the hybrid broadcast signal to produce an analog audio stream and a digital audio stream; and using a normalized cross-correlation of envelopes of the analog audio stream and the digital audio stream to measure a time offset between the analog audio stream and the digital audio stream. The time offset can be used to align the analog audio stream and the digital audio stream for subsequent blending of an output of the radio receiver from the analog audio stream to the digital audio stream or from the digital audio stream to the analog audio stream.

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.