A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

The present invention relates to a method and an apparatus for automatic skew compensation. The apparatus according to the present invention comprises: a skew compensating part configured to receive a high speed data signal and output a plurality of delay data signals having different delay times; a start code detecting part configured to detect a start code from the plurality of delay data signals; and a control part configured to determine a skew delay time depending on signal reception quality which is determined on the basis of the number of start codes normally detected for each different delay time. The apparatus may further comprise a packet start detecting part configured to receive an LP signal separated from an MIPI D-PHY and count the number of received packets. The packet start detecting part receives the LP signal separated from the MIPI D-PHY, and counts the number of packets received at every preset quality evaluation time by detecting the start location of a packet according to the state of the LP signal. The signal reception quality is obtained using the number of normally detected start codes and the number of received packets received and counted at every quality evaluation time. The present invention can automatically compensate the skew between a data signal and a clock signal in an MIPI D-PHY reception system.

A device includes a receiver to receive a packet over a channel at a first frequency and generate a sampled stream of data at a first sample rate corresponding to the first frequency. A data resampler circuit includes a re-timer engine to determine, using a fractional rate between the first sample rate and a crystal oscillator (XO)-divided sample rate, re-timer values including a difference between pulses of a pseudo clock corresponding to the XO-integer-divided sample rate and closest corresponding pulses of a clock corresponding to the first sample rate. The data resampler circuit includes a time shifting circuit to re-sample data values of the sampled stream of data associated with locations of the plurality of re-timer values. A correlation circuit uses the re-sampled data values, pseudo clock, and the re-timer values to match an expected data pattern to a corresponding data pattern detected in a frame delimiter of the packet.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft?, Overwatch?, H1Z1?, PUBG?, Fortnite?, Realm Royale?, Planet Side 2?, real-time strategy games, slot machines, electronic poker tournaments, etc.

A clock synchronization apparatus, an optical transmitter, an optical receiver, and a clock synchronization method are provided. In the clock synchronization apparatus, a digital interpolator adjusts a sampling clock frequency of a digital signal under sampling clock control of a clock control circuit.

First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

The present invention pertains to a method for configuring an infrared audio transmission system comprising a signal generator and a plurality of radiators connected to said signal generator, the method comprising at least one of said plurality of radiators: receiving (1050) a delay compensation configuration message; and storing (1060) an amount of delay to be introduced into subsequently radiated signals in accordance with the received delay compensation configuration message. The invention also pertains to a configuration node (100) for configuring radiators in such a system, configured to: transmit (1010) at least one test signal to the radiators; detect (1020) events triggered by the test signal; determine (1030) respective transmission delays between the node and the radiators on the basis of these reflections; and transmit (1040) a delay compensation configuration message over said network, the delays being included in the delay compensation configuration message.

A time-based decision feedback equalizer (TB-DFE) circuit may include a voltage-to-time converter configured to convert a communication signal into a time-based signal. A timing of when an edge of the time-based signal occurs is indicative of a voltage level of the communication signal. The circuit may include a plurality of delay circuits arranged to process the time-based signal in series to generate a delay data signal. The delay circuits may adjust the timing of when the edge of the time-based signal occurs, and a corresponding time delay introduced by each of the delay circuits may be based on a respective weighting factor applied to one or more samples of an output digital signal previously generated by the TB-DFE circuit. A phase detector may compare a timing of an edge of the delay data signal with a reference clock signal and generate the output digital signal based on the comparison.

The present invention provides a receiver, wherein the receiver includes a plurality of receiving circuit and a skew detection and alignment circuit. The receiving circuit is arranged for receiving a plurality of input signals from a plurality of channels, wherein each of the receiving circuits receives at least one of the input signals to generate an output signal. The skew detection and alignment circuit is arranged for determining skew information according to at least one of the input signals and the output signals, wherein the skew information is used to control delay amounts corresponding to the input signals or the output signals.