A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.

A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.

A transmitter circuit includes a phase locked loop circuit, having one or more operational characteristics indicative of an operating state of the phase locked loop circuit. The phase locked loop circuit is configured to generate a frequency signal. The transmitter circuit also includes a power amplifier configured to selectively drive an antenna with a drive signal according to the frequency signal, and a programmable delay circuit configured to controllably extend a propagation delay between the frequency signal and the drive signal of the power amplifier. The programmable delay circuit is programmed such that a first value of a particular operational characteristic of the phase locked loop circuit is substantially equal to a second value of the operational characteristic of the phase locked loop circuit. The first value is measured with the power amplifier not driving the antenna. The second value is measured with the power amplifier driving the antenna.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft®, Overwatch®, H1Z1®, PUBG®, Fortnite®, Realm Royale®, Planet Side 2®, real-time strategy games, slot machines, electronic poker tournaments, etc.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

Disclosed is a frequency swept source apparatus including a mode locking laser that outputs an input optical signal having first to n-th frequency components, a transmission delay controller that generates first to m-th sub-optical signals, each of which includes at least one component of the first to n-th frequency components, and outputs a delay optical signal obtained by sequentially delaying the first to m-th sub-optical signals. The transmission delay controller includes a demultiplexer that outputs the first to m-th sub-optical signals to first to m-th channels based on the input optical signal, respectively, a path delay unit that adjusts lengths of optical paths of the first to m-th channels so as to be different from one another, a refractive index controller that adjusts a refractive index of each of the first to m-th channels, and a multiplexer that combines the first to m-th sub-optical signals.

An asynchronous data capture device comprises an edge spread detector circuit, a clock generator, and a data sampling circuit. The edge spread detector circuit uses a first clock frequency that is a multiple of a second clock frequency, identifies transitions in a data stream transmitted to the device at the second clock frequency, and determines a sampling point based on the identified transitions. The clock generator adjusts a phase offset based on the sampling point and generates a clock signal having the second clock frequency and the adjusted phase offset. The data sampling circuit uses the second clock frequency and samples the data stream at the sampling point. In some implementations, the edge spread detector determines a sampling point that is isolated from the identified transitions, and the clock generator adjusts the phase offset to cause a rising edge at the sampling point.

A device with wireless communication includes: an input receiver configured to receive an input signal having a carrier frequency; a delay circuit configured to generate a delayed signal by delaying the input signal; and a clock generator configured to generate a clock signal having a clock frequency based on the delayed signal and the input signal.

In examples, a sensor device is adapted to be coupled, by a shared power and data connection (SPDC), to other sensor devices in a chain of sensor devices. The sensor device comprises a sensor to sense a parameter, a counter, and a controller coupled to the sensor and the counter. The controller is configured to determine, based on an index position of the sensor device, a time that is to elapse between receipt of a command to convert the sensed parameter to a digital code and a conversion of the sensed parameter to the digital code. The controller is configured to, responsive to receipt of the command, set the counter to the time. The controller is configured to convert the sensed parameter to the digital code upon the counter indicating that the time has elapsed.

A method for processing audio signals in a radio transmitter, includes: receiving an analog audio sample stream and a digital audio sample stream; determining offsets in time between the analog audio stream and the digital audio stream using a normalized cross-correlation of audio envelopes of the analog audio sample stream and the digital audio sample stream; filtering the determined offsets in time to produce filtered offset values; determining an alignment slip adjustment value as a function of the filtered offset values; aligning the analog audio sample stream and the digital audio sample stream using the determined alignment slip adjustment value; and generating a hybrid radio signal for broadcast that includes time-aligned analog audio and digital audio.