A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Disclosed is a frequency swept source apparatus including a mode locking laser that outputs an input optical signal having first to n-th frequency components, a transmission delay controller that generates first to m-th sub-optical signals, each of which includes at least one component of the first to n-th frequency components, and outputs a delay optical signal obtained by sequentially delaying the first to m-th sub-optical signals. The transmission delay controller includes a demultiplexer that outputs the first to m-th sub-optical signals to first to m-th channels based on the input optical signal, respectively, a path delay unit that adjusts lengths of optical paths of the first to m-th channels so as to be different from one another, a refractive index controller that adjusts a refractive index of each of the first to m-th channels, and a multiplexer that combines the first to m-th sub-optical signals.

First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft®, Overwatch®, H1Z1®, PUBG®, Fortnite®, Realm Royale®, Planet Side 2®, real-time strategy games, slot machines, electronic poker tournaments, etc.

Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft®, Overwatch®, H1Z1®, PUBG®, Fortnite®, Realm Royale®, Planet Side 2®, real-time strategy games, slot machines, electronic poker tournaments, etc.

A receiver includes a first receiving circuit that receives a first data including a first symbol transmitted using three signals over a first data lane, the first data lane including three signal lines respectively corresponding to the three signals. The first receiving circuit includes a delay adjustment circuit configured to adjust a delay amount of at least one of the three signals.

A clock synchronization apparatus, an optical transmitter, an optical receiver, and a clock synchronization method are provided. In the clock synchronization apparatus, a digital interpolator adjusts a sampling clock frequency of a digital signal under sampling clock control of a clock control circuit.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft®, Overwatch®, H1Z1®, PUBG®, Fortnite®, Realm Royale®, Planet Side 2®, real-time strategy games, slot machines, electronic poker tournaments, etc.

A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.