A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

A method for processing a digital audio broadcast signal in a radio receiver, includes: receiving a hybrid broadcast signal; demodulating the hybrid broadcast signal to produce an analog audio stream and a digital audio stream; and using a normalized cross-correlation of envelopes of the analog audio stream and the digital audio stream to measure a time offset between the analog audio stream and the digital audio stream. The time offset can be used to align the analog audio stream and the digital audio stream for subsequent blending of an output of the radio receiver from the analog audio stream to the digital audio stream or from the digital audio stream to the analog audio stream.

The present invention relates to a network packet relay device including a time synchronization module for synchronizing a time of a packet with a timestamp value of a network device, and a packet timestamp assigning method thereof, wherein a timestamp having accuracy of a UTC-format nanosecond level can be assigned to the packet at a hardware level by correcting overflow of a register of an elapsed-time counter of a processor of a switch even when the overflow occurs.

The present invention relates to: a network packet intermediary device comprising a deep packet matching module for matching a GTP control plane packet and a GTP user plane packet by controlling a GTP correlation module; and a deep packet matching method thereof, and can extract packet information of a deep step from a switch level so as to match flows of the GTP control plane packet and. the GTP user plane packet, and can provide a correlation so that the GTP control plane packet and the GTP user plane packet can be transmitted to the same outlet port.

One exemplary aspect relates to normalizing latency in a networking environment to reduce the chances of creating an unfair advantage. While an exemplary aspect will be discussed in relation to a gaming environment, it is to be appreciated that the techniques disclosed herein can be applied to other environments where latency normalization or the ability to maintain latency between various endpoints is desired. For example, other environments include eSporting, on-line betting, fantasy esports, streaming services, etc. Some more specific examples include World of Warcraft®, Overwatch®, H1Z1®, PUBG®, Fortnite®, Realm Royale®, Planet Side 2®, real-time strategy games, slot machines, electronic poker tournaments, etc.

The present disclosure relates to an in-vehicle communication device and a time synchronization method thereof. The in-vehicle communication device includes a clock generator for generating a clock signal, a local counter for counting the number of pulses of the clock signal, a transceiver for receiving a message via an in-vehicle communication network, and a processor that determines whether the message received via the transceiver is a synchronization message, extracts synchronization time information from the synchronization message, and adjusts a count value of the local counter based on the synchronization time information to perform time synchronization.

A method is provided for synchronizing a source device with a sink device. The source device transmits a stream of packets to the sink device. The source device receives feedback from the sink device indicating packet arrival times of the packets at the sink device. Based on the feedback, in some aspects, the source device determines an average time shift in the packet arrival times at the sink device, wherein the average time shift is relative to expected packet arrival times of the packets at the sink device. In some such aspects, the source device detects that the average time shift exceeds a threshold, and in response to the detecting, adjusts a streaming time of the stream of packets to synchronize, within a predefined tolerance, the source device with the sink device.

A code acquisition module for a direct sequence spread spectrum (DSSS) receiver includes: a Sparse Discrete Fourier transform (SDFT) module configured to perform an SDFT on a finite number of non-uniformly distributed frequencies comprising a preamble of a received DSSS frame to calculate Fourier coefficients for the finite number of non-uniformly distributed frequencies; a multiplier configured to multiply the Fourier coefficients for the finite number of non-uniformly distributed frequencies of the received DSSS frame by complex conjugate Fourier coefficients for the finite number of non-uniformly distributed frequencies to generate a cross-correlation of the received DSSS frame and the complex conjugate Fourier coefficients; and a filter module configured to input the cross-correlation and output a delay estimation for the received DSSS frame.

A signaling system is disclosed. The signaling system includes a first integrated circuit (IC) chip to receive a data signal and a strobe signal. The first IC includes circuitry to sample the data signal at times indicated by the strobe signal to generate phase error information and circuitry to output the phase error information from the first IC device. The system further includes a signaling link and a second IC chip coupled to the first IC chip via the signaling link to output the data signal and the strobe signal to the first IC chip. The second IC chip includes delay circuitry to generate the strobe signal by delaying an aperiodic timing signal for a first time interval and timing control circuitry to receive the phase error information from the first IC chip and adjust the first time interval in accordance with the phase error information.

The present invention discloses a method for configuring an operation mode of a remote transceiver unit connected to an access node via a communication line, the remote transceiver unit being operable in at least two operation modes: a Time Division Duplex, TDD, mode and a full duplex, FDX, mode; the method comprising, by the access node: a) obtaining a channel characteristic derived from channel measurements performed over the communication line, b) determining the operation mode of the remote transceiver unit as the FDX mode or the TDD mode based on the channel characteristic; c) transmitting an indication indicating the determined operation mode to the remote transceiver unit.