A femtocell telecommunication system equipment comprising: a base apparatus structured to provide a first information signal and control signals; an electrical conductor based transmission line connected to said base apparatus; a bidirectional conversion apparatus adapted to receive/transmit from/on the transmission line the first signal and the control signals; the bidirectional apparatus comprising: a processing module structured to process the first signal to generate a second information signal and vice-versa; the second signal being adapted to be transmitted/received by an antenna device connectable to the bidirectional apparatus.

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

In certain aspects of the present disclosure an apparatus for wireless communication comprises a processing system and an interface. The processing system is configured to generate a preamble and a first data portion of a frame, wherein the preamble includes information for receiving the frame at a device, receive a message from the device, wherein the message provides feedback of reception of the first data portion by the device, and generate a second data portion of the frame. The interface is configure to output the preamble and the first data portion of the frame for transmission to the device, and output the second data portion of the frame for transmission to the device, wherein transmission of the first and second data portions of the frame are separated in time by a gap, and the message is received within the gap.

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

A clock data recovery apparatus includes an oscillator, a phase detector and an oscillator control circuit. The oscillator generates an original clock signal. The phase detector includes a first sampling circuit, a frequency dividing circuit, a second sampling circuit and a selecting circuit. The first sampling circuit samples a data signal using the original clock signal to generate a first set of sample results. The frequency dividing circuit divides the original clock signal to generate a frequency divided clock signal. The second sampling circuit performs sampling using the frequency divided clock signal to generate a second set of sample results. The selecting circuit selectively outputs one of the first and second sets of sample results as a final set of sample results. The oscillator control circuit controls the oscillator according to the final set of sample results.

A femtocell telecommunication system equipment comprising: a base apparatus structured to provide a first information signal and control signals; an electrical conductor based transmission line connected to said base apparatus; a bidirectional conversion apparatus adapted to receive/transmit from/on the transmission line the first signal and the control signals; the bidirectional apparatus comprising: a processing module structured to process the first signal to generate a second information signal and vice-versa; the second signal being adapted to be transmitted/received by an antenna device connectable to the bidirectional apparatus.