A circuit includes a serializer module that includes an input stage that samples an input signal to capture an edge location for each of the input signal in a given time frame. An edge encoder encodes the edge location for the input signal into a packet frame to specify where the edge location occurs in the given time frame for the input signal. A transmitter receives the packet frame from the edge decoder and converts the packet frame into a serial data stream. The transmitter communicates the edge location for the input signal via the serial data stream.

Systems and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS) and determining a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses based on the correlated CP signals.

Apparatuses and methods of manufacturing same, systems, and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS); measuring power variation of the received signal in the frequency domain based on the plurality of hypotheses of SCS; and combining weighted results of a correlation of the CP signals in the time domain and the measured power variation in the frequency domain to determine a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses.

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

Various examples are provided for jamming avoidance response (JAR), and photonic implementations thereof. In one example, a method includes generating optical pulses that correspond to raising envelope of a beat signal associated with an interference signal and a reference signal; generating optical spikes that correspond to positive zero crossing points of the reference signal; and providing a phase output that indicates whether the beat signal is leading or lagging the reference signal, the phase output based at least in part upon the optical spikes. An adjustment to a reference frequency can be determined based at least in part upon the optical pulses and the phase output. In another example, a JAR system includes photonic circuitry to generate the optical pulses; photonic circuitry to generate the optical spikes; and photonic circuitry to provide the phase output. A logic unit can determine the adjustment to the reference frequency.

Apparatuses and methods of manufacturing same, systems, and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS); measuring power variation of the received signal in the frequency domain based on the plurality of hypotheses of SCS; and combining weighted results of a correlation of the CP signals in the time domain and the measured power variation in the frequency domain to determine a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses.

An optical channel between a coherent optical transmitter and a coherent optical receiver may include one or more components that act as a bandpass filter with a passband that is narrower than the signal bandwidth. Such a narrow filter may significantly attenuate the signal content close to the band edge of the data signal. As a result, timing error detection may work less effectively, and therefore clock recovery may be less effective or fail. Methods and systems are disclosed in which a single optical carrier is used to transmit a data signal that has multiple bands, and timing error detection is performed at the receiver using one or more inner bands of the multiple bands. The timing error detection may therefore be made more robust to the effects of the narrow filtering.

An optical channel between a coherent optical transmitter and a coherent optical receiver may include one or more components that act as a bandpass filter with a passband that is narrower than the signal bandwidth. Such a narrow filter may significantly attenuate the signal content close to the band edge of the data signal. As a result, timing error detection may work less effectively, and therefore clock recovery may be less effective or fail. Methods and systems are disclosed in which a single optical carrier is used to transmit a data signal that has multiple bands, and timing error detection is performed at the receiver using one or more inner bands of the multiple bands. The timing error detection may therefore be made more robust to the effects of the narrow filtering.

A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.