A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.

Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data.

In a clock data recovery circuit according to related art, it is difficult to achieve a high responsiveness. According to one embodiment, a clock data recovery circuit includes a loop filter, the loop filter including a first path (121, 122) that determines a loop gain that sets a speed of adjusting a phase of a recovery clock to a phase of an input signal, a second path (123, 124) that determines a frequency tracking gain that sets a speed of adjusting a frequency of the recovery clock to a frequency of the input signal, and a compensator 130 that gives a negative feedback from an output side to an input side of the first path and compensates for a phase delay of an output of a phase detector due to a delay amount of the loop filter.

The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

In order to determine a temporal offset between a first signal at a first signal input and a second signal at a second signal input, a first momentary value of a first continuous signal trace, which rises strictly monotonically in a first early signal subperiod and falls strictly monotonically to zero in a first late signal subperiod and which is the first signal or is generated therefrom, is multiplied by a second momentary value of a derivative with respect to time of a second continuous signal trace, which rises strictly monotonically in a second early signal subperiod and falls strictly monotonically to zero in a second late signal subperiod and which is the second signal or generated therefrom, whereby a signal product is obtained. The signal product is integrated over time. Thus, a signal integral is obtained, which indicates the temporal offset of the first signal to the second signal.