A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

A sensor may determine a sampling pattern based on a group of synchronization signals received by the sensor. The sampling pattern may identify an expected time for receiving an upcoming synchronization signal. The sensor may trigger, based on the sampling pattern, a performance of a sensor operation associated with the upcoming synchronization signal. The performance of the sensor operation may be triggered before the upcoming synchronization signal is received.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

Embodiments are disclosed for full-rate phase detection for a pulse amplitude modulation N (PAM-N) signal. The example method includes sampling an incoming signal in one or more sampling times. The example method further includes determining that an amplitude associated with a current sampling time is within an upper threshold and a lower threshold for each sampling time of the one or more sampling times. The example method further includes upon determining that the amplitude of the current sampling time is within the upper threshold and the lower threshold, determining an amplitude range associated with an immediately preceding sampling time and an amplitude range associated with an immediately subsequent sampling time. The example method further includes determining a transition status representing one of an upward transition, a downward transition, or no transition with respect to the current sampling time.

A clock data recovery (CDR) mechanism qualifies symbols received from the data detector prior to using those symbols to compute a timing gradient. The disclosed CDR mechanism analyzes one or more recently received symbols to determine whether the current symbol should be used in computing the time gradient. When configured with a Mueller-Muller phase detector, the timing gradient for the received signal is set to zero if the current symbol is a 2 or a +2 and the previous symbol is non-zero. Otherwise, the Mueller-Muller timing gradient is evaluated in the traditional manner. When configured with a minimum mean-squared error phase detector, the timing gradient for the received signal is set to zero if the previous symbol is non-zero. Otherwise, the minimum mean-squared error timing gradient is evaluated in the traditional manner.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

A receiving apparatus includes a first sample circuit configured to extract first binary data based on a first voltage and a clock timing of a received signal, a second sample circuit configured to extract second binary data based on an adjustable second voltage and a clock timing of the received signal, and a waveform processor configured to acquire a plurality of the second binary data from the second sample circuit using a pattern, the pattern corresponding to the first binary data extracted by the first sample circuit with consecutive sampling timings, determine an appearance frequency of the received signal based on the plurality of second binary data and the first binary data, and generate waveform information of the received signal according to the determined appearance frequency.

According to one embodiment, a semiconductor integrated circuit includes: an equalizer circuit; a decision circuit that decides a bit value of a data signal; a sampler unit including sampler circuits, the sampler circuits having different thresholds and electrically connected in parallel between the equalizer circuit and the decision circuit; a determination circuit that determines indexes indicating a degree of confidence of current output values from the sampler circuits based on the bit values of the data signals at different past timings; and an arithmetic circuit that computes scores for bit values that are candidates for a current data signal based on the determined indexes and current output values from the sampler circuits. The decision circuit selects one bit value from the candidate bit values using the scores.

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.