Phase detectors for clock and data recovery circuits are provided herein. In certain implementations, a phase detector includes sampling circuitry that generates a plurality of samples of an input data signal based on timing of a plurality of clock signals, a binary response circuit that processes the plurality of samples to generate a plurality of binary output signals providing a binary detector response, and a linear response circuit that processes the plurality of samples to generate a plurality of linear output signals providing a linear detector response. The phase detector generates one or more data output signals based on the plurality of samples to thereby recover data from the input data signal.

Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method includes recovering a first clock signal from transitions between pairs of symbols representative of successive signaling states of a 3-wire interface, where a pulse in the first clock signal is generated in response to an earliest-occurring transition between the first and second symbols in one of three difference signals representative of differences in state between two wires, determining direction of voltage change of a first transition detected on a first difference signal, providing a value selected based on the direction of voltage change as value of the first difference signal in the second symbol, and providing a value of a second difference signal captured during the first symbol as the value of the second difference signal when the second difference signal does not transition between the first symbol and the second symbol.

A clock and data recovery (CDR) circuit includes a phase detector, a digital loop filter, and a lock detector. The phase detector generates a phase detect result signal in response to phase detection of a plurality of samples. The plurality of samples are generated by sampling a received signal based on a sampling clock a sampling clock provided by a phase interpolator. The digital loop filter includes a phase path and a frequency path for providing a phase path correction signal and a frequency path correction signal based on the phase detect result signal respectively. A phase interpolator code generator generates a phase interpolator code for controlling the phase interpolator based on the phase path correction signal and frequency path correction signal. The lock detector generates a lock condition signal based on the frequency path correction signal, the lock condition signal indicating a lock condition of the CDR circuit.

A frequency synthesizer 11a outputs a periodic signal r(t) at a frequency detuned by a predetermined frequency f [Hz] from a frequency of 1/integer of a frequency of a reference clock signal f0 synchronized with a signal to be measured ws. A first sampler unit 12 samples the signal to be measured ws at a timing of the trigger signal CLK. A second sampler unit 13a samples an I signal I(t) at the timing of the trigger signal CLK. A phase shifter 13b outputs a Q signal Q(t) obtained by shifting a phase of the reference clock signal f0 by 90. A third sampler unit 13c samples the Q signal at the timing of the trigger signal CLK. A correction value calculation unit 13d calculates a correction value t(n) based on sampling data I(n) and Q(n) and a set value t(n) of a sampling time.

A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.

A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.

Timing recovery systems and methods can include receiving a signal with Nyquist shaped pulses, sampling the signal using an analog-to-digital converter at a sampling rate, generating a plurality of delayed sampled signals from the received pulses, resampling each delayed sampled signal to 1 sample per symbol, taking the absolute value of each resampled signal, raising the absolute value of each resampled signal to the fourth power, taking the mean of the fourth power of the absolute value of each resampled signal, feeding all of the mean values into a phase estimator, and using the output from the phase estimator for timing correction. The output from the phase estimator can either be fed back to the analog-to-digital converter, or to an interpolation stage that adjusts sampling instants of the sampled signals output from the analog-to-digital converter, to correct the timing.

A semiconductor integrated circuit includes a clock recovery circuit that receive a multi-level pulse-amplitude modulated signal and to recover a clock signal. The clock recovery circuit includes a generation circuit and an oscillator. The generation circuit includes a plurality of comparators and pulse generators and a pulse summing circuit. The plurality of comparators and pulse generators compare the multi-level pulse-amplitude modulated signal with a plurality of threshold values to generate a plurality of pulses according to a plurality of comparison results. The pulse summing circuit generates a synthetic pulse based on the generated plurality of pulses. The oscillator oscillates in synchronization with the synthetic pulse to generate the clock signal.

Systems and methods for processing data including a first and second component are described. An example circuit includes a processing stage arranged to calculate absolute values of the first component and the second component, and to output, at a first output, a maximum value of the absolute value of the first component and the absolute value of the second component, and, at a second output, a minimum value of the absolute value of the first component and the absolute value of the second component. The circuit includes a processing stage arranged to output, in response to the maximum value being greater than the minimum value times four, a value corresponding to the maximum value, and to output, in response to the maximum value being smaller than the minimum value times four, a value corresponding to a sum of seven times the maximum value and four times the minimum value.

Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.