Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

A clock generator circuit includes: first to N.sup.th nodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to N.sup.th nodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to N.sup.th nodes have a first level, and the signals of odd-numbered nodes among the first to N.sup.th nodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to N.sup.th nodes have the same level.

A jitter measuring setup (10) comprises a signal generator (14), a sample-and-hold circuit (15), and the inventive all stochastic jitter measuring device (1) comprising signal acquisition means (2) and calculation means (3). The input signal of the sample-and-hold circuit (15) is generated by the signal generator (14). Furthermore, the output signal of the sample-and-hold circuit (15), respectively the input signal of the measuring device (1), is comprised of a superposition of the sampled input signal of the sample-and-hold circuit (15) and a cyclostationary random process.

A system for synthetically sampling an input signal to provide a sampled signal includes a sample clock and a mixer. The sample clock is configured to generate a sampling signal having a sampling frequency. The mixer is configured to receive the sampling signal and the input signal, and to output an intermediate frequency (IF) signal by mixing the sampling signal and the input signal. An offset voltage is introduced into the mixer with the sampling signal to provide a baseband image, the offset voltage being adjusted so that the baseband image of the IF signal has the same magnitude as a first harmonic image of the IF signal.

An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.

A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.

Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer.