There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

A receiver includes a sampling circuit configured to sample a comparison result between an input signal and a plurality of threshold voltages according to a sampling clock signal; a clock controller configured to generate the sampling clock signal according to a clock control signal; and a control circuit configure to generate the clock control signal and the plurality of threshold voltages according to a target value and an output of the sampling circuit. The control circuit operates to control a ratio of a magnitude of a main cursor of the input signal and a magnitude of a pre-cursor intersymbol interference to be the target value.

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.

A clock and data recovery circuit includes a phase interpolation circuit that adjusts a phase of a reference clock signal generated by a reference clock generation circuit to generate a reception clock signal, a filter that performs filter processing on a data signal output from an ADC that converts an analog data signal to a digital data signal in synchronization with the clock signal, a phase comparison circuit that outputs phase difference data between a transmission-side clock signal and the reference clock signal based on an output of the filter, and a loop filter that generates phase data to be set in the phase interpolation circuit. The filter includes an FIR filter with a tap number N, and an FIR filter with a tap number N+1 that outputs a signal delayed by half a clock than the former FIR filter.

A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

A method for configuring a time division duplex (TDD) of a user equipment in a communication system, according to one embodiment of the present invention, comprises the steps of: receiving from a base station a first TDD configuration; receiving from the base station a message including information related to a dynamic TDD configuration; receiving a second TDD configuration according to the received information related to the dynamic TDD configuration; receiving from the base station an uplink grant; and determining whether to apply the first TDD configuration or the second TDD configuration based on a method by which the unlink grant is received. According to one embodiment of the present invention, the advantages of configuring a shorter cycle of the TDD to the user equipment supporting the TDD in a wireless communication system, and rapidly configuring the TDD to the user equipment variably according to a communication situation are provided.

Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

A method includes receiving, at a radar timing card, radar timing information and a synchronous clock signal. The method also includes generating, using the radar timing card, a timing trigger to indicate a time of transmission for radar return information. The method further includes receiving, at each of multiple digital-to-analog converter (DAC) channels of one or more DAC cards, the synchronous clock signal and the timing trigger. In addition, the method includes simultaneously transmitting, from each of the DAC channels, a dedicated portion of the radar return information based on the time of transmission indicated by the timing trigger. The synchronous clock signal is used to align the simultaneous transmissions of the DAC channels on the one or more DAC cards.