Patent classifications
H04L7/042
Variable Rate Sampling in a Bluetooth Receiver using Connection Status
A Bluetooth receiver has an RF front end which has a gain control input, the RF front end converting wireless packets into a baseband signal which is coupled to the input of an analog to digital converter (ADC). A clock generator provides a clock coupled to the ADC, and an AGC processor performs an AGC process to provide a gain which places the baseband symbols in a range that is less than 90% of the input dynamic range of the ADC. When in a connected state, the clock generator provides a clock which is slower than is required to complete the AGC process during a preamble interval, and the AGC process uses a few initial bits of the address field. The remaining bits of the address field is compared with the corresponding address bits of the receiver to determine whether to receive the packet.
Packet detecting method of a wireless signal and packet detecting system of the wireless signal capable of identifying adjacent channel interference
A packet detecting method includes receiving the wireless signal, generating a local characteristic sequence, acquiring a first cross-correlation result between the wireless signal and the local characteristic sequence, determining if a packet format of the wireless signal is a target packet format according to the first correlation result, generating at least one interference characteristic sequence according to the local characteristic sequence, a signal sampling frequency, and at least one working frequency difference, acquiring a second cross-correlation result between the wireless signal and the at least one interference characteristic sequence, and detecting a center frequency of the wireless signal for determining if a packet of the wireless signal is transmitted through a target channel according to the first correlation result and the second correlation result. The at least one interference characteristic sequence corresponds to at least one interference frequency.
Circuit of communication interface between two dies and method to manage communication interface
A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.
Low-complexity synchronization header detection
A technique of separating a sequence of modulation shift keying (MSK) symbols into a first portion and a second portion and separately comparing the first portion of the sequence of MSK symbols and the second portion of the sequence of MSK symbols against a first portion of a reference sequence of MSK symbols and a second portion of the reference sequence of MSK symbols allows a low complexity detection of a start field delimiter in a wireless communication packet.
Multi-lane serializer device
A multi-lane serializer device 1 includes serializer circuits 10.sub.1 to 10.sub.N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.
Frame synchronization apparatus, optical communication apparatus, and frame synchronization method
A frame synchronization apparatus (10) according to this invention includes a multiplication unit (11) configured to multiply a received signal by an inverse complex number of a predetermined synchronization pattern with respect to a predetermined signal point on a complex space diagram for each of a plurality of symbols of the received signal, an addition average unit (12) configured to perform addition averaging of outputs from the multiplication unit for the plurality of symbols of the received signal, and a synchronization determination unit (13) configured to perform coincidence determination of whether an output from the addition average unit (12) falls within a predetermined coincidence determination range of the predetermined signal point, and determine a synchronization state of the frame synchronization based on a result of the coincidence determination. According to this invention, it is possible to provide a frame synchronization apparatus that correctly determines a synchronization state even if an error rate of received symbols is high.
SYMBOL GENERATION AND FRAME SYNCHRONIZATION FOR MULTIPULSE-PULSE POSITION MODULATION
A method and system for multipulse-pulse position modulation optical transmission that includes selecting a multipulse-pulse position modulation having a symbol alphabet having an upper-bound symbol alphabet size, and determining, based on at least one transmission characteristic associated with a transmitter, a subset of symbols of the selected symbol alphabet capable of being transmitted by the transmitter, the subset of symbols having a set of binary codewords. The method and system may include identifying two-symbol concatenation of binary codewords in the set of binary codewords, calculating a cross correlation of binary codeword in the set of binary code words through every two-symbol concatenation, determining a set of one or more acceptable codeword combinations by eliminating a portion of two-symbol concatenation of codewords corresponding to overlapping peaks in the respective calculated cross correlations, and transmitting, by the transmitter via an optical communication channel, information encoded based on the determined acceptable codeword combinations.
Systems and methods for synchronize word correlation
Systems and methods for synchronize word correlation. The methods comprise: obtaining first values that each indicate a likelihood or probability that a respective timeslot in a symbol timing window of a carrier wave is meant or expected to include energy; multiplying, by the correlator, the first values respectively by correlation coefficients to produce a plurality of products (wherein at least one of the correlation coefficients comprises a negative coefficient value); generating a correlation value by combining the products together; determining whether a synchronization word has been detected with a given amount of likelihood based on the correlation value; and causing symbol timing synchronization at a receiver when a determination is made that the synchronization word has been detected with the given amount of likelihood based on the correlation value.
RECEIVER CIRCUIT AND METHOD CAPABLE OF ACCURATELY ESTIMATING TIME OFFSET OF SIGNAL
A method applicable to a receiver circuit, including: performing a cross-correlation operation upon at least one time-domain signal on at least one receiver path of the receiver circuit according to a local sequence signal, to estimate at least one time offset amount of the at least one time-domain signal as at least one time offset compensation amount; and, performing time offset compensation upon the at least one time-domain signal on the at least one receiver path according to the at least one time offset compensation amount.
Method and apparatus for performing non-unique data pattern detection and alignment in a receiver implemented on a field programmable gate array
A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.