A method of communicating between nodes in a network where a node receives a sequence of symbols that will form a packet on a first communications channel and has a planned packet that it would send on a second communications channel. A destination is encoded into an arbitration portion of a header sequence of the packet, the header sequence comprising a sequence of symbols. The transmission on the second communications channel is as per the planned packet, for as long as the symbols of the planned packet match the symbols being received on the first channel. An arbitration decision is made when the symbols do not match, with the node either continuing to send the rest of the planned packet, or the rest of the packet being received on the first communications channel.

A physical layer (PHY) device comprises a phase interpolator to generate a set of sampler clocks. A sampler of the PHY device samples a calibration data pattern based on the set of sampler clocks. A data alignment system of the PHY device performs a coarse calibration and a fine calibration on the sampler clock signals. During the coarse calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on a first bit of the sampled data. During the fine calibration, the data alignment system moves the sampler clock signals earlier or later in time relative to the sampled data based on the first bit, a second bit, and a third bit in the sampled data.

Systems, methods, and apparatuses are discussed that enable robust, high-speed communication of sensor data. One example system includes a sensor bus, an electronic control unit (ECU), and one or more sensors. The ECU is coupleable to the sensor bus and configured to generate a synchronization signal, and is configured to output the synchronization signal to the sensor bus. The one or more sensors are also coupleable to the sensor bus, and at least one sensor of the one or more sensors is configured to sample sensor data in response to the synchronization signal and to output the sampled sensor data to the sensor bus.

A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

Systems, methods, and apparatuses are discussed that enable robust, high-speed communication of sensor data. One example system includes a sensor bus, an electronic control unit (ECU), and one or more sensors. The ECU is coupleable to the sensor bus and configured to generate a synchronization signal, and is configured to output the synchronization signal to the sensor bus. The one or more sensors are also coupleable to the sensor bus, and at least one sensor of the one or more sensors is configured to sample sensor data in response to the synchronization signal and to output the sampled sensor data to the sensor bus.

A restraint control module is provided in this disclosure. The restraint control module is configured to communicate a sync pulse to a sensor. The control module may include a sync pulse driver circuit and a memory. The memory may store the waveform profile of a sync pulse. The sync pulse driver circuit generates a sync pulse in response to the waveform profile stored in the memory. The sync pulse may be transmitted to one or more sensors. The waveform profile stored in the memory may be derived from a sync pulse with reduced electro-magnetic emissions by applying spectrum analysis.

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

In generating a mask signal used to recover a clock signal embedded in an interface signal, the mask signal may be generated by comparing a plurality of comparison signals, generated by delaying a plurality of mask rising signals by a predetermined time, with the clock signal and selecting one mask rising signal used to generate a comparison signal close to one portion of the clock signal from among the plurality of mask rising signals.

Systems, methods, and apparatus for transmitting additional information over a synchronous serial bus are described. A method performed at a transmitting device coupled to the serial bus includes providing first data in a data signal to be transmitted on a first wire of a multi-wire serial bus, providing a series of pulses in a clock signal to be transmitted on a second wire of a multi-wire serial bus, where each pulse has a rising edge and a falling edge, each edge being aligned with a different bit of the first data. The method may include encoding second data in the clock signal by controlling a duration of each pulse in the series of pulses based on a value of one or more bits of the second data, and transmitting the data signal and the clock signal over the serial bus.

The present disclosure relates to a circuit for calibrating a baud rate. The circuit includes: a first counter connected to a receiving module of a serial port chip and configured to record a first low level duration of a data frame received by the receiving module; a second counter configured to: receive a bit sampling pulse generated from sampling the data frame according to a current baud rate of the receiving module, and record a quantity of the bit sampling pulse in the first low level duration; a divider, connected to the first counter and the second counter and calculate a calibration baud rate according to the first low level duration and the quantity of the bit sampling pulse in the first low level duration; and a selector, connected to the receiving module and the divider and configured to output the calibration baud rate to the receiving module.